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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Nonvolatile Memristive Effect in Few-Layer CrI 3 Driven by Electrostatic Gating

The potential of memristive devices for applications in nonvolatile memory and neuromorphic computing has sparked considerable interest, particularly in exploring memristive effects in two-dimensional (2D) magnetic materials. However, the progress in developing nonvolatile, magnetic field-free memristive devices using 2D magnets has been limited. In this work, we report an electrostatic-gating-induced nonvolatile memristive effect in CrI 3 -based tunnel junctions. The few-layer CrI 3 -based tunnel junction manifests notable hysteresis in its tunneling resistance as a function of gate voltage. We further engineered a nonvolatile memristor using the CrI 3 tunneling junction with low writing power and at zero magnetic field. We show that the hysteretic transport observed is not a result of trivial effects or inherent magnetic properties of CrI 3 . We propose a potential association between the memristive effect and the newly predicted ferroelectricity in CrI 3 via gating-induced Jahn–Teller distortion. Furthermore, our work illuminates the potential of 2D magnets in developing next-generation advanced computing technologies.

2D magnet↗
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2025

Kelvin Probe Force Microscopy Imaging of Plasticity in Hydrogenated Perovskite Nickelate Multilevel Neuromorphic Devices

Ion drift in nanoscale electronically inhomogeneous semiconductors is among the most important mechanisms being studied for designing neuromorphic computing hardware. However, nondestructive imaging of the ion drift in operando devices directly responsible for multiresistance states and synaptic memory represents a formidable challenge. Here, we present Kelvin probe force microscopy imaging of hydrogen-doped perovskite nickelate device channels subject to high-speed electric field pulses to directly visualize proton distribution by monitoring surface potential changes spatially, which is also supported with finite element-based electric field distribution studies. First-principles calculations provide mechanistic insights into the origin of surface potential changes as a function of hydrogen donor doping that serves as the contrast mechanism. We demonstrate 128 (7-bit) nonvolatile conductance levels in such devices relevant to in-memory computing applications. The synaptic plasticity measurements are implemented in spiking neural networks and show promising results for classification (SciKit Learn’s Iris and Wine data sets) and control (OpenAI’s CartPole-v1 and BipedalWalker-v3) simulation tasks.

Kelvin probe force microscopy↗
DOE OSTI2025

Short-Term Forecasting of Thermostatic and Residential Loads Using Long Short-Term Memory Recurrent Neural Networks

Internet of Things (IoT) devices in smart grids enable intelligent energy management for grid managers and personalized energy services for consumers. Investigating a smart grid with IoT devices requires a simulation framework with IoT devices modeling. However, there lack comprehensive study on the modeling of IoT devices in smart grids. This paper investigates the IoT device modeling of a thermostatic load and implements the recurrent neural networks model for short-term load forecasting in this IoT-based thermostatic load. The recurrent neural network structure is leveraged to build a load forecasting model on temporal correlation. The temporal recurrent neural network layers including long short-term memory cells are employed to learn the data from both the simulation platform and New South Wales residential datasets. The simulation results are provided for demonstration.

electric load forecasting↗
DOE OSTI2020

Beyond Substrates: Strain Engineering of Ferroelectric Membranes

Strain engineering in perovskite oxides provides for dramatic control over material structure, phase, and properties, but is restricted by the discrete strain states produced by available high-quality substrates. Here, using the ferroelectric BaTiO3, production of precisely strain-engineered, substrate-released nanoscale membranes is demonstrated via an epitaxial lift-off process that allows the high crystalline quality of films grown on substrates to be replicated. In turn, fine structural tuning is achieved using interlayer stress in symmetric trilayer oxide-metal/ferroelectric/oxide-metal structures fabricated from the released membranes. Additionally, in devices integrated on silicon, the interlayer stress provides deterministic control of ordering temperature (from 75 to 425 °C) and releasing the substrate clamping is shown to dramatically impact ferroelectric switching and domain dynamics (including reducing coercive fields to <10 kV cm-1 and improving switching times to <5 ns for a 20 µm diameter capacitor in a 100-nm-thick film). In devices integrated on flexible polymers, enhanced room-temperature dielectric permittivity with large mechanical tunability (a 90% change upon ±0.1% strain application) is demonstrated. This approach paves the way toward the fabrication of ultrafast CMOS-compatible ferroelectric memories and ultrasensitive flexible nanosensor devices, and it may also be leveraged for the stabilization of novel phases and functionalities not achievable via direct epitaxial growth.

36 MATERIALS SCIENCE↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS1990

Solid-state thin-film memistor for electronic neural networks

This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Thakoor, S.↗
DOE OSTI2022

PUF-Based Two-Factor Authentication Protocol for Securing the Power Grid Against Insider Threat

Recent advances in smart grid technologies have enabled additional distributed control paradigms that allow more efficient and reliable operation. However, this creates new security concerns for the grid, such as attackers using spoofed grid control devices to generate false measurements. This paper introduces a two-factor authentication protocol leveraging standard public-key cryptography as one authentication factor and a hardware-based fingerprint, known as a Physical Unclonable Function, as a second authentication factor. This protocol incurs a small overhead and prevents cyber-attacks even when an adversary is able to compromise the cryptographic keys stored in the non-volatile memory of an intelligent control device.

42 ENGINEERING↗
NASA NTRS1987

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of the second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗
NASA NTRS1989

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗
NASA NTRS2001

A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.

Green, M. L.↗
DOE OSTI2023

Independent malware detection architecture

A system and method (referred to as the system) detect malware by training a rule-based model, a functional based model, and a deep learning-based model from a memory snapshot of a malware free operating state of a monitored device. The system extracts a feature set from a second memory snapshot captured from an operating state of the monitored device and processes the feature set by the rule-based model, the functional-based model, and the deep learning-based model. The system identifies identifying instances of malware on the monitored device without processing data identifying an operating system of the monitored device, data associated with a prior identification of the malware, data identifying a source of the malware, data identifying a location of the malware on the monitored device, or any operating system specific data contained within the monitored device.

Smith, Jared M.↗
DOE OSTI2023

Apparatus and methods for managing packet transfer across a memory fabric physical layer interface

An apparatus and method for managing packet transfer between a memory fabric having a physical layer interface higher data rate than a data rate of a physical layer interface of another device, receives incoming packets from the memory fabric physical layer interface wherein at least some of the packets include different instruction types. The apparatus and method determine a packet type of the incoming packet received from the memory fabric physical layer interface and when the determined incoming packet type is of a type containing an atomic request, the method and apparatus prioritizes transfer of the incoming packet with the atomic request over other packet types of incoming packets, to memory access logic that accesses local memory within an apparatus.

Blagodurov, Sergey↗
NASA NTRS1985

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Nelson, G. L.↗
NASA NTRS2015

Shape Memory Alloy Rock Splitters (SMARS) - A Non-Explosive Method for Fracturing Planetary Rocklike Materials and Minerals

A static rock splitter device based on high-force, high-temperature shape memory alloys (HTSMAs) was developed for space related applications requiring controlled geologic excavation in planetary bodies such as the Moon, Mars, and near-Earth asteroids. The device, hereafter referred to as the shape memory alloy rock splitter (SMARS), consisted of active (expanding) elements made of Ni50.3Ti29.7Hf20 (at.%) that generate extremely large forces in response to thermal input. The preshaping (training) of these elements was accomplished using isothermal, isobaric and cyclic training methods, which resulted in active components capable of generating stresses in excess of 1.5 GPa. The corresponding strains (or displacements) were also evaluated and were found to be 2 to 3 percent, essential to rock fracturing and/or splitting when placed in a borehole. SMARS performance was evaluated using a test bed consisting of a temperature controller, custom heaters and heater holders, and an enclosure for rock placement and breakage. The SMARS system was evaluated using various rock types including igneous rocks (e.g., basalt, quartz, granite) and sedimentary rocks (e.g., sandstone, limestone).

NiTiHf↗
NASA NTRS1991

Formal verification of an MMU and MMU cache

We describe the formal verification of a hardware subsystem consisting of a memory management unit and a cache. These devices are verified independently and then shown to interact correctly when composed. The MMU authorizes memory requests and translates virtual addresses to real addresses. The cache improves performance by maintaining a LRU (least recently used) list from the memory resident segment table.

Schubert, E. T.↗
NASA NTRS2008

Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same

Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Kaul, Anupama B.↗
DOE OSTI2025

High-Resolution Full-Field Structural Microscopy of the Voltage-Induced Filament Formation in VO 2 -Based Neuromorphic Devices

In order to make neuromorphic functions in memristive devices more efficient, information about the structural properties of filament formation at the micro- and mesoscopic scales is necessary. Despite extensive research on VO 2 , a key material due to its filament formation, local operando structural measurements remain challenging and often involve destructive specimen preparation and long rastering times, greatly limiting the scope of experimental studies. Utilizing dark-field X-ray microscopy (DFXM), a fullfield imaging modality, structural signatures of the filament formation process operando are revealed in VO 2 devices. DFXM experiments illustrate that rutile filaments contain isolated monoclinic clusters, indicating structural nonuniformity interior to the filament. The formation of the rutile phase beneath device electrodes was shown to precede filament development, followed by the formation of filament paths guided by nucleation sites within the device. Finally, a medium-term (<30 min) memory mechanism is observed in VO 2 , mediated by sites within the device gap that tend to switch at significantly lower voltages after electrical cycling, a tendency that persists through a brief thermal reset. High spatial resolution, large field-of-view, structure selectivity, and fast signal acquisition of DFXM provided insight into structural features of the filamentary channel and surrounding regions during voltage cycling.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗