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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Microhard MHX 2420 Orbital Performance Evaluation Using RT Logic T400CS

A major upfront cost of building low cost Nanosatellites is the communications sub-system. Most radios built for space missions cost over $4,000 per unit. This exceeds many budgets. One possible cost effective solution is the Microhard MHX2420, a commercial off-the-shelf transceiver with a unit cost under $1000. This paper aims to support the Nanosatellite community seeking an inexpensive radio by characterizing Microhard's performance envelope. Though not intended for space operations, the ability to test edge cases and increase average data transfer speeds through optimization positions this radio as a solution for Nanosatellite communications by expanding usage to include more missions. The second objective of this paper is to test and verify the optimal radio settings for the most common cases to improve downlinking. All tests were conducted with the aid of the RT Logic T400CS, a hardware-in-the-loop channel simulator designed to emulate real-world radio frequency (RF) link effects. This study provides recommended settings to optimize the downlink speed as well as the environmental parameters that cause the link to fail.

Microhard MHX 2420↗
NASA NTRS1984

On the utilization of engineering knowledge in design optimization

Some current research work conducted at the University of Michigan is described to illustrate efforts for incorporating knowledge in optimization in a nontraditional way. The incorporation of available knowledge in a logic structure is examined in two circumstances. The first examines the possibility of introducing global design information in a local active set strategy implemented during the iterations of projection-type algorithms for nonlinearly constrained problems. The technique used algorithms for nonlinearly constrained problems. The technique used combines global and local monotinicity analysis of the objective and constraint functions. The second examines a knowledge-based program which aids the user to create condigurations that are most desirable from the manufacturing assembly viewpoint. The data bank used is the classification scheme suggested by Boothroyd. The important aspect of this program is that it is an aid for synthesis intended for use in the design concept phase in a way similar to the so-called idea-triggers in creativity-enhancement techniques like brain-storming. The idea generation, however, is not random but it is driven by the goal of achieving the best acceptable configuration.

Papalambros, P.↗
NASA NTRS2008

Cassini's Maneuver Automation Software (MAS) Process: How to Successfully Command 200 Navigation Maneuvers

To keep Cassini on its complex trajectory, more than 200 orbit trim maneuvers (OTMs) have been planned from July 2004 to July 2010. With only a few days between many of these OTMs, the operations process of planning and executing the necessary commands had to be automated. The resulting Maneuver Automation Software (MAS) process minimizes the workforce required for, and maximizes the efficiency of, the maneuver design and uplink activities. The MAS process is a well-organized and logically constructed interface between Cassini's Navigation (NAV), Spacecraft Operations (SCO), and Ground Software teams. Upon delivery of an orbit determination (OD) from NAV, the MAS process can generate a maneuver design and all related uplink and verification products within 30 minutes. To date, all 112 OTMs executed by the Cassini spacecraft have been successful. MAS was even used to successfully design and execute a maneuver while the spacecraft was in safe mode.

Yang, Genevie Velarde↗
NASA NTRS1972

Conceptual design and analysis of an infared horizon sensor with compensation for atmospheric variability

A horizon detection logic, based on a ratio-of-integrated-radiance concept, which detects the earth's horizon at a relatively stable height under all geographic and meteorological conditions was evaluated by computer simulation on a body of synthesized radiance profiles. An error-sensitivity analysis of the concept was performed, and optimum design parameter values for a sensor were determined. A conceptual design for an improved 15 micron sensor based on this analysis is discussed.

Jalink, A., Jr.↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
NASA NTRS2002

An Embedded Reconfigurable Logic Module

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

Tucker, Jerry H.↗
NASA NTRS1992

Flexible body control using neural networks

Progress is reported on the control of Control Structures Interaction suitcase demonstrator (a flexible structure) using neural networks and fuzzy logic. It is concluded that while control by neural nets alone (i.e., allowing the net to design a controller with no human intervention) has yielded less than optimal results, the neural net trained to emulate the existing fuzzy logic controller does produce acceptible system responses for the initial conditions examined. Also, a neural net was found to be very successful in performing the emulation step necessary for the anticipatory fuzzy controller for the CSI suitcase demonstrator. The fuzzy neural hybrid, which exhibits good robustness and noise rejection properties, shows promise as a controller for practical flexible systems, and should be further evaluated.

Mccullough, Claire L.↗
NASA NTRS1993

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Fura, David A.↗
DOE OSTI2022

A multi-stage single photochrome system for controlled photoswitching responses

The ability of molecular photoswitches to convert on/off responses into large macroscale property change is fundamental to light-responsive materials. However, moving beyond simple binary responses necessitates the introduction of new elements that control the chemistry of the photoswitching process at the molecular scale. To achieve this goal, we designed, synthesized and developed a single photochrome, based on a modified donor–acceptor Stenhouse adduct (DASA), capable of independently addressing multiple molecular states. The multi-stage photoswitch enables complex switching phenomena. To demonstrate this, we show spatial control of the transformation of a three-stage photoswitch by tuning the population of intermediates along the multi-step reaction pathway of the DASAs without interfering with either the first or final stage. This allows for a photonic three-stage logic gate where the secondary wavelength solely negates the input of the primary wavelength. Finally, these results provide a new strategy to move beyond traditional on/off binary photochromic systems and enable the design of future molecular logic systems.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2007

Improved On-Chip Measurement of Delay in an FPGA or ASIC

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chen, Yuan↗
DOE OSTI2020

Logic in Memory Emulator

Logic in Memory Emulator (LiME) is a hardware/software tool specially designed for memory system evaluation and experiment. Emerging memories display a wide range of bandwidths, latencies, and capacities, making it challenging for the computer architect to navigate the design space of potential memory configurations, and for the application developer to assess performance implications of using such memories. With the LiME framework, architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. LiME consists of two fundamental components: 1) the hardware and OS infrastructure for the emulator, and 2) a suite of benchmark applications to assist in characterizing the performance of current and future computer architectures. Some of the applications have been collected from other open source projects. Uses: Logging, replay and analysis of an application's memory behavior Evaluate impact of emerging memory technology on application performance. Emulate complex memory interactions in whole applications orders of magnitude faster than software simulation. Emulate acceleration hardware co-located with the memory subsystem. Features: Capture and log external memory accesses to a separate off-chip memory device without affecting application execution. Memory traces include the address, length, timestamp, and optionally the data for each transaction. Captured trace data can be saved to an SD card for off-line analysis. Configure a wide range of memory latencies in sub-nanosecond increments that encompass highbandwidth and storage class memories. Specify regions of interest (ROI) in applications to reduce the amount of trace data captured for analysis. Currently supports execution on Xilinx Zynq SoC which integrates an ARM processor with FPGA logic on a single device. Applications can be run under Linux or in bare metal mode on the ARM cores.

Jain, AbhishekK↗
NASA NTRS1994

Inner loop flight control for the High-Speed Civil Transport

High-speed aerospace vehicles which employ high strength, light weight, yet deformable materials may exhibit significant interaction between the rigid-body and vibrational dynamics. Preliminary High-Speed Civil Transport (HSCT) configurations are a prime example. Traditionally, separate control systems have been used to augment the rigid-body and vibrational dynamics. In the HSCT arena, the highly coupled motions may not allow this design freedom. The research activity addresses two specific issues associated with the design and development of an integrated flight control system (FCS) for HSCT configurations, which are discussed next. The HSCT is expected to have a short period instability at subsonic speeds. Flight vehicles with this characteristic (i.e., F-16, F-22, X-29, Space Shuttle) are stabilized with what is called a superaugmented pitch rate loop. One concern is 'Will this stability augmentation logic work for a HSCT?' Studies show that an idealized pitch rate design would be acceptable, but is not realistic. Investigations using a contaminated pitch rate design reveal serious hurdles to overcome in the FCS design. Mounting location for the pitch rate sensor is critical. Results indicate a forward location leads to destabilizing pick-up of aeroelastic modes, while aft locations lead to undesirable coupling of the dominate pitch mode with the first aeroelastic mode. Intermediate locations for the sensor may not be acceptable. The source of the problem is the presence of low frequency aeroelastic modes in HSCT configurations, which are not present in vehicles currently using the superaugmented logic. To say the least, a conventional superaugmented pitch rate loop strategy may have undesirable characteristics. An unconventional strategy, which attempts to eliminate the above deficiencies by blending several pitch rate signals, indicates an improvement in the FCS architecture feasibility, but is still lacking in some respects. The HSCT configuration does not have aerodynamic surfaces in the vicinity of the nose (i.e., no canard or vane). A second concern is 'Can the fuselage bending/torsion aeroelastic modes be effectively augmented without sufficient control input near the vehicle nose?' The superaugmented FCS results above may be suggesting the necessity of a secondary feedback loop to achieve an acceptable integrated FCS. Preliminary analysis of HSCT aeroelastic mode shapes indicate the use of existing wing leading edge devices as a second control input may be lacking in control authority for the rigid-body attitude and aeroelastic modes. An effort is underway to incorporate generic wing leading edge devices and canards into a generic HSCT model for the purpose of assessing additional control authority and it's use in candidate FCS designs. A generic HSCT mathematical model was necessary for the studies above. A HSCT category model is available in NASA-CR-172201. This model describes the linear, longitudinal dynamics about the following flight condition: ascent, W = 730,000 lbs, h = 6,500 ft, M = 0.6. The model incorporates the full rigid-body variable set, as well as eighteen aeroelastic modes. Elevator deflection serves as the control input. Modifications to the model include the incorporation of relaxed static stability (i.e., static margin from -7.3% to +10%) and additional control inputs.

Newman, Brett A.↗
NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗
NASA NTRS1976

Digital controllers for VTOL aircraft

Using linear-optimal estimation and control techniques, digital-adaptive control laws have been designed for a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. Two distinct discrete-time control laws are designed to interface with velocity-command and attitude-command guidance logic, and each incorporates proportional-integral compensation for non-zero-set-point regulation, as well as reduced-order Kalman filters for sensor blending and noise rejection. Adaptation to flight condition is achieved with a novel gain-scheduling method based on correlation and regression analysis. The linear-optimal design approach is found to be a valuable tool in the development of practical multivariable control laws for vehicles which evidence significant coupling and insufficient natural stability.

Stengel, R. F.↗
NASA NTRS1990

A bit serial sequential circuit

Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.

Hu, S.↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗
NASA NTRS1993

Three-dimensional flow in radial turbomachinery and its impact on design

In the two papers on the 'Theory of Blade Design for Large Deflections' published in 1984, a new inverse design technique was presented for designing the shape of turbomachinery blades in three-dimensional flow. The technique involves the determination of the blade profile from the specification of a distribution of the product of the radius and the pitched averaged tangential velocity (i.e., r bar-V(sub theta), the mean swirl schedule) within the bladed region. This is in contrast to the conventional inverse design technique for turbomachinery blading in two dimensional flow in which the blade surface pressure or velocity distribution is specified and the blade profile determined as a result; this is feasible in two-dimensional flow because the streamlines along the blade surfaces are known a priori. However, in three-dimensional flow, the stream surface is free to deform within the blade passage so that the streamlines on the blade surfaces are not known a priori; thus it is difficult and not so useful to prescribe the blade surface pressure or velocity distribution and determine the resulting blade profile. It therefore seems logical to prescribe the swirl schedule within the bladed region for designing a turbomachinery blade profile in three-dimensional flow. Furthermore, specifying r bar-V(sub theta) has the following advantages: (1) it is related to the circulation around the blade (i.e., it is an aerodynamic quantity); (2) the work done or extracted is approximately proportional to the overall change in r bar-V(sub theta) across a given blade row (Euler turbine equation); and (3) the rate of change of r bar-V(sub theta) along the mean streamline at the blade is related to the pressure jump across the blade and therefore the blade loading. Since the publications of those two papers, the technique has been applied to the design of a low speed as well as a high speed radial inflow turbine (for turbocharger applications) both of which showed definite improvements in performance over that of wheels of conventional designs, the design study of a high pressure ratio radial inflow turbine with and without splitter blades.

Tan, Choon S.↗
NASA NTRS1987

SOLON: An autonomous vehicle mission planner

The State-Operator Logic Machine (SOLON) Planner provides an architecture for effective real-time planning and replanning for an autonomous vehicle. The highlights of the system, which distinguish it from other AI-based planners that have been designed previously, are its hybrid application of state-driven control architecture and the use of both schematic representations and logic programming for the management of its knowledge base. SOLON is designed to provide multiple levels of planning for a single autonomous vehicle which is supplied with a skeletal, partially-specified mission plan at the outset of the vehicle's operations. This mission plan consists of a set of objectives, each of which will be decomposable by the planner into tasks. These tasks are themselves comparatively complex sets of actions which are executable by a conventional real-time control system which does not perform planning but which is capable of making adjustments or modifications to the provided tasks according to constraints and tolerances provided by the Planner. The current implementation of the SOLON is in the form of a real-time simulation of the Planner module of an Intelligent Vehicle Controller (IVC) on-board an autonomous underwater vehicle (AUV). The simulation is embedded within a larger simulator environment known as ICDS (Intelligent Controller Development System) operating on a Symbolics 3645/75 computer.

Dudziak, M. J.↗