Design of fault-tolerant computers.
Logic fault tolerant digital computer design for increased reliability, discussing logic circuits and protective redundancy
Avizienis, A.↗
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Results for “Digital circuits”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Switching circuits with fast response and low power drain
New logic circuits have response times no longer than 10 nanoseconds and drain only milliwatts of power. The family includes AND and NAND gates and forms the basis of all logic functions. The basic circuits are used in various types of digital-data-processing systems.
Cancro, C. A.↗
Nonvolatile read/write memory element - A concept
Memory, with limited number of programming cycles, is achieved by using verticle, fusible links in series with oxide breakthrough elements. Memory elements are fabricated with integrated circuit technology and are ideal for low power digital computer application.
Cricchi, J. R.↗
Drive circuit utilizing two cores Patent
Reliable magnetic core circuit apparatus with application in selection matrices for digital memories
Zottarelli, L. J.↗
Rate-of-change limiter for quantized signals
Analog circuit is employed to smooth change between levels of quantized voltage signal without adversely affecting its fidelity. Circuit is applicable to units requiring interface between digital and analog systems such as automated manufacturing systems or industrial robots.
Streuding, G. C.↗
Synthesis and implementation of state-trajectory control law for dc-to-dc converters
Mathematical representations of a state-plane switching boundary employed in a state-trajectory control law for dc-to-dc converters are derived. Two approaches to implementing the control law are discussed; one approach employs a digital processor and the other uses analog computational circuits. Performance characteristics of experimental voltage step-up dc-to-dc converters operating under the control of each of these implementations are presented.
Burns, W. W., III↗
Fast-response free-running dc-to-dc converter employing a state-trajectory control law
A recently proposed state-trajectory control law for a family of energy-storage dc-to-dc converters has been implemented for the voltage step-up configuration. Two methods of realization are discussed; one employs a digital processor and the other uses analog computational circuits. Performance characteristics of experimental voltage step-up converters operating under the control of each of these implementations are reported and compared to theoretical predictions and computer simulations.
Huffman, S. D.↗
Smoothing the output from a DAC
Circuit smooths stepped waveform from analog-to-digital converter without appreciable phase shift between stepped input signal and smoothed output signal and without any effect from stepping rate. Waveform produced is suitable for driving controls used in manufacturing processes, aerospace systems, and automobiles.
Wagner, C.↗
A novel demodulator/detector for digital and analog signals on LMR channels
The design, implementation, and performance of an all-digital demodulator/detector suitable for differentially encoded phase-shift keying (DPSK), continuous-phase frequency-shift keying (CPFSK), frequency-shift keying (FSK), and analog FM are discussed. In this demodulator/detector, two detectors, one noncoherent and another differentially coherent, operate simultaneously to provide data detection and automatic frequency control (AFC). Test results indicate that the system provides improved performance over the conventional analog quadrature detector for two-period raised-cosine (2RC) CPFSK modulation in additive white Gaussian noise (AWGN) and Rayleigh fading channels. Being all-digital, the demodulator/detector is well suited for integrated circuit implementation. In addition, the system performs as well as the analog quadrature detector for analog FM voice transmissions, thereby maintaining full compatibility with analog land mobile radio (LMR) transmissions.
Saulnier, Gary J.↗
Integration and test of high-speed transmitter electronics for free-space laser communications
The NASA Lewis Research Center in Cleveland, Ohio, has developed the electronics for a free-space, direct-detection laser communications system demonstration. Under the High-Speed Laser Integrated Terminal Electronics (Hi-LITE) Project, NASA Lewis has built a prototype full-duplex, dual-channel electronics transmitter and receiver operating at 325 megabit S per second (Mbps) per channel and using quaternary pulse-position modulation (QPPM). This paper describes the integration and testing of the transmitter portion for future application in free-space, direct-detection laser communications. A companion paper reviews the receiver portion of the prototype electronics. Minor modifications to the transmitter were made since the initial report on the entire system, and this paper addresses them. The digital electronics are implemented in gallium arsenide integrated circuits mounted on prototype boards. The fabrication and implementation issues related to these high-speed devices are discussed. The transmitter's test results are documented, and its functionality is verified by exercising all modes of operation. Various testing issues pertaining to high-speed circuits are addressed. A description of the transmitter electronics packaging concludes the paper.
Soni, Nitin J.↗
Artifacts Of Spectral Analysis Of Instrument Readings
Report presents experimental and theoretical study of some of artifacts introduced by processing outputs of two nominally identical low-frequency-reading instruments; high-sensitivity servo-accelerometers mounted together and operating, in conjunction with signal-conditioning circuits, as seismometers. Processing involved analog-to-digital conversion with anti-aliasing filtering, followed by digital processing including frequency weighting and computation of different measures of power spectral density (PSD).
Wise, James H.↗
Radiation Tolerant Intelligent Memory Stack (RTIMS)
The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.
Ng, Tak-kwong↗
Room and Low Temperature Performance of High-Speed Neural Network Circuits
We have described a challenging neural-network hardware implementation that would mate a 64x64-pixel infrared sensor directly on to a 3-dimensionally packaged set of neural processing chips with parallel input for high speed image processing. Non linearity effects and range compression are also discussed.
high-speed neural network circuits neural network ↗
Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications
This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.
active pixel image sensors CMOS signal processing ↗
Continuous-Integration Laser Energy Lidar Monitor
This circuit design implements an integrator intended to allow digitization of the energy output of a pulsed laser, or the energy of a received pulse of laser light. It integrates the output of a detector upon which the laser light is incident. The integration is performed constantly, either by means of an active integrator, or by passive components.
Karsh, Jeremy↗
Radiation-Tolerant Intelligent Memory Stack - RTIMS
This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware
Ng, Tak-kwong↗
Space-Based Reconfigurable Software Defined Radio Test Bed Aboard International Space Station
The National Aeronautical and Space Administration (NASA) recently launched a new software defined radio research test bed to the International Space Station. The test bed, sponsored by the Space Communications and Navigation (SCaN) Office within NASA is referred to as the SCaN Testbed. The SCaN Testbed is a highly capable communications system, composed of three software defined radios, integrated into a flight system, and mounted to the truss of the International Space Station. Software defined radios offer the future promise of in-flight reconfigurability, autonomy, and eventually cognitive operation. The adoption of software defined radios offers space missions a new way to develop and operate space transceivers for communications and navigation. Reconfigurable or software defined radios with communications and navigation functions implemented in software or VHDL (Very High Speed Hardware Description Language) provide the capability to change the functionality of the radio during development or after launch. The ability to change the operating characteristics of a radio through software once deployed to space offers the flexibility to adapt to new science opportunities, recover from anomalies within the science payload or communication system, and potentially reduce development cost and risk by adapting generic space platforms to meet specific mission requirements. The software defined radios on the SCaN Testbed are each compliant to NASA's Space Telecommunications Radio System (STRS) Architecture. The STRS Architecture is an open, non-proprietary architecture that defines interfaces for the connections between radio components. It provides an operating environment to abstract the communication waveform application from the underlying platform specific hardware such as digital-to-analog converters, analog-to-digital converters, oscillators, RF attenuators, automatic gain control circuits, FPGAs, general-purpose processors, etc. and the interconnections among different radio components.
Communications↗
Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment
This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar pressure. The prototype package is based on previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degC Earth air ambient for over ten thousands hours, and short-term tested at temperatures above 800 degC. The three-phase harsh environment test started with 48 hours in 465 degC Earth air, followed by 48 hours in 465 degC nitrogen at 90 bar pressure and 1400 hours in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar. Initial analytical results of the package materials and surfaces after exposure to Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.
Chen, Liangyu↗