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At least 487 records · Page 27

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NASA NTRS1986

PbS-PbSe IR detector arrays

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Barrett, John R.↗

NASA NTRS2008

Integral resonator gyroscope

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Shcheglov, Kirill V.↗

NASA NTRS2009

SOI CMOS Imager with Suppression of Cross-Talk

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata↗

NASA NTRS2008

Four-Point-Latching Microactuator

An experimental inchworm-type linear microactuator is depicted. This microactuator is a successor to one described in "MEMS-Based Piezoelectric/Electrostatic Inchworm Actuator" (NPO-30672), NASA Tech Briefs, Vol. 27, No. 6 (June 2003), page 68. Both actuators are based on the principle of using a piezoelectric transducer operated in alternation with electrostatically actuated clutches to cause a slider to move in small increments. However, the design of the present actuator incorporates several improvements over that of the previous one. The most readily apparent improvement is in geometry and, consequently, in fabrication: In the previous actuator, the inchworm motion was perpendicular to the broad faces of a flat silicon wafer on which the actuator was fabricated, and fabrication involved complex processes to form complex three-dimensional shapes in and on the wafer. In the present actuator, the inchworm motion is parallel to the broad faces of a wafer on which it is fabricated. The components needed to produce the in-plane motion are nearly planar in character and, consequently, easier to fabricate. Other advantages of the present design are described, including that the previous actuator contained two clutches (denoted 'holders' in the cited prior article), the present actuator contains four clutches. The operational sequence of the previous two-clutch actuator is similar. However, the two-clutch configuration is susceptible to tilt of the slider and a consequent large increase in drag. Hence, the primary operational advantages of the present four-point-latching design over the prior two-point-latching design are less drag and greater control robustness arising from greater stability of the orientation of the slider.

Toda, Risaku↗

NASA NTRS2009

Fabrication of an Antenna-Coupled Bolometer for Cosmic Microwave Background Polarimetry

We describe the development of a detector for precise measurements of the cosmic microwave background polarization. The detector employs a waveguide to couple light between a pair of Mo/Au superconducting transition edge sensors (TES) and a feedhorn. Incorporation of an on-chip ortho-mode transducer (OMT) results in high isolation. The OMT is micromachined and bonded to the microstrip and TES circuits in a low temperature wafer bonding process. The wafer bonding process incorporates a buried superconducting niobium layer with a single crystal silicon layer which serves as the leg isolated TES membrane and as the microstrip dielectric. We describe the micromachining and wafer bonding process and report measurement results of the microwave circuitry operating in the 29-43GHz band along with Johnson noise measurements of the TES membrane structures and development of Mo/Au TES operating under '00mK.

Denis, K.L.↗

NASA NTRS2007

Calligraphic Poling of Ferroelectric Material

Calligraphic poling is a technique for generating an arbitrary, possibly complex pattern of localized reversal in the direction of permanent polarization in a wafer of LiNbO3 or other ferroelectric material. The technique is so named because it involves a writing process in which a sharp electrode tip is moved across a surface of the wafer to expose the wafer to a polarizing electric field in the desired pattern. The technique is implemented by use of an apparatus, denoted a calligraphic poling machine (CPM), that includes the electrode and other components as described in more detail below.

Mohageg, Makan↗

NASA NTRS2007

Process for High-Rate Fabrication of Alumina Nanotemplates

An anodizing process, at an early stage of development at the time of reporting the information for this article, has shown promise as a means of fabricating alumina nanotemplates integrated with silicon wafers. Alumina nanotemplates are basically layers of alumina, typically several microns thick, in which are formed approximately regular hexagonal arrays of holes having typical diameters of the order of 10 to 100 nm. Interest in alumina nanotemplates has grown in recent years because they have been found to be useful as templates in the fabrication of nanoscale magnetic, electronic, optoelectronic, and other devices. The present anodizing process is attractive for the fabrication of alumina nanotemplates integrated with silicon wafers in two respects: (1) the process involves self-ordering of the holes; that is, the holes as formed by the process are spontaneously arranged in approximately regular hexagonal arrays; and (2) the rates of growth (that is, elongation) of the holes are high enough to make the process compatible with other processes used in the mass production of integrated circuits. In preparation for fabrication of alumina nanotemplates in this process, one first uses electron-beam evaporation to deposit thin films of titanium, followed by thin films of aluminum, on silicon wafers. Then the alumina nanotemplates are formed by anodizing the aluminum layers, as described below. In experiments in which the process was partially developed, the titanium films were 200 A thick and the aluminum films were 5 m thick. The aluminum films were oxidized to alumina, and the arrays of holes were formed by anodizing the aluminum in aqueous solutions of sulfuric and/or oxalic acid at room temperature (see figure). The diameters, spacings, and rates of growth of the holes were found to depend, variously, on the composition of the anodizing solution, the applied current, or the applied potential, as follows: In galvanostatically controlled anodizing, regardless of the chemical composition of the solution, relatively high current densities (50 to 100 mA/cm2) resulted in arrays of holes that were more nearly regular than were those formed at lower current densities. . The rates of elongation of the holes were found to depend linearly on the applied current density: the observed factor of proportionality was 1.2 (m/h)/(mA/cm2). For a given fixed current density and room temperature, the hole diameters were found to depend mainly on the chemical compositions of the anodizing solutions. The holes produced in sulfuric acid solutions were smaller than those produced in oxalic acid solutions. The arrays of holes produced in sulfuric acid were more ordered than were those produced in oxalic acid. . The breakdown voltage was found to decrease logarithmically with increasing concentration of sulfuric acid. The breakdown voltage was also found to decrease with temperature and to be accompanied by a decrease in hole diameter. The hole diameter was found to vary linearly with applied potential, with a slope of 2.1 nm/V. This slope differs from slopes (2.2 and 2.77 nm/V) reported for similar prior measurements on nanotemplates made from bulk aluminum. The differences among these slopes may be attributable to differences among impurities and defects in bulk and electron-beam-evaporated aluminum specimens.

Myung, Nosang↗

NASA NTRS2007

Microrectenna: A Terahertz Antenna and Rectifier on a Chip

A microrectenna that would operate at a frequency of 2.5 THz has been designed and partially fabricated. The circuit is intended to be a prototype of an extremely compact device that could be used to convert radio-beamed power to DC to drive microdevices (see Figure 1). The microrectenna (see Figure 2) circuit consists of an antenna, a diode rectifier and a DC output port. The antenna consists of a twin slot array in a conducting ground plane (denoted the antenna ground plane) over an enclosed quarter-wavelength-thick resonant cavity (denoted the reflecting ground plane). The circuit also contains a planar high-frequency low-parasitic Schottky-barrier diode, a low-impedance microstrip transmission line, capacitors, and contact beam leads. The entire 3-D circuit is fabricated monolithically from a single GaAs wafer. The resonant cavity renders the slot radiation pattern unidirectional with a half-power beam width of about 65. A unique metal mesh on the rear of the wafer forms the backplate for the cavity but allows the GaAs to be wet etched from the rear surface of the twin slot antennas and ground plane. The beam leads protrude past the edge of the chip and are used both to mount the microrectenna and to make the DC electrical connection with external circuitry. The antenna ground plane and the components on top of it are formed on a 2- m thick GaAs membrane that is grown in the initial wafer MBE (molecular beam epitaxy) process. The side walls of the antenna cavity are not metal coated and, hence, would cause some loss of power; however, the relatively high permittivity (epsilon=13) of the GaAs keeps the cavity modes well confined, without the usual surface-wave losses associated with thick dielectric substrates. The Schottky-barrier diode has the usual submicron dimensions associated with THz operation and is formed in a mesa process above the antenna ground plane. The diode is connected at the midpoint of a microstrip transmission line, which is formed on 1- m-thick SiO (permittivity of 5) laid down on top of the GaAs membrane. The twin slots are fed in phase by this structure. To prevent radio-frequency (RF) leakage past the slot antennas, low-loss capacitors are integrated into the microstrip transmission line at the edges of the slots. The DC current- carrying lines extend from the outer edges of the capacitors, widen approaching the edges of the chip, and continue past the edges of the chip to become the beam leads used in tacking down the devices. The structure provides a self-contained RF to DC converter that works in the THz range.

Siegel, Peter↗

NASA NTRS2007

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata↗

NASA NTRS2010

Solar cell circuit and method for manufacturing solar cells

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Mardesich, Nick↗

NASA NTRS2010

Disc resonator gyroscope fabrication process requiring no bonding alignment

A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

Shcheglov, Kirill V.↗

NASA NTRS2003

MEMS-Based Piezoelectric/Electrostatic Inchworm Actuator

A proposed inchworm actuator, to be designed and fabricated according to the principles of microelectromechanical systems (MEMS), would effect linear motion characterized by steps as small as nanometers and an overall range of travel of hundreds of microns. Potential applications for actuators like this one include precise positioning of optical components and active suppression of noise and vibration in scientific instruments, conveyance of wafers in the semiconductor industry, precise positioning for machine tools, and positioning and actuation of micro-surgical instruments. The inchworm motion would be generated by a combination of piezoelectric driving and electrostatic clamping. The actuator (see figure), would include a pair of holders (used for electrostatic clamping), a slider (the part that would engage in the desired linear motion), a driver, a piezoelectric stack under the driver, and a pair of polymer beams centrally clamped to the flexure beam via a T bar. The holders would be held stationary. One end of the piezoelectric stack would be held stationary; the other end would be connected to the bottom of the driver, which would be free to move up and down. All of these components except the piezoelectric stack and the polymer beams would be micromachined from a 500- m-thick silicon wafer by deep reactive-ion etching. The inchworm motion would be perpendicular to the broad faces of the wafer (perpendicular to the plane of the figure). The combination of the polymer beams and the centrally clamped flexure beam would spring-bias the slider into a position such that, in the absence of electrostatic clamping, the gap between the slider on the one hand and both the driver and the holder on the other hand would be no more than a few microns. This arrangement would make it possible to electrostatically pull the slider into contact with either the holders or the driver at a clamping force of the order of 1 N by applying a reasonably small voltage (of the order of 100 V).

Yang, Eui-Hyeok↗

NASA NTRS2003

Electrical Characterization and Morphological Studies of Conducting Polymer Nanofibers

Doped polyaniline blended with poly(ethylene oxide) has been electrospun in air to give fibers with diameters in the range 3 nm 200 nm. These fibers were captured on wafers of degenerately doped Si/SiO2 by placing the wafer in the path of the fiber jet formed during the electrospinning process. Individual fibers were contacted using shadow mask evaporation and were also captured on prepatterned wafers. Fibers having diameters greater than 100 nm show a slight increase in the conductivity as compared to the bulk film, while fibers with diameters less than 30 nm had lower conductivity than the bulk. Data on Scanning Conductance Microscopy along the length of individual fibers will be presented. For fibers where the diameter was not uniform, we found that below a certain diameter ( approx.15 nm) the fiber was less conducting as compared to thicker diameter fibers. Dependence of the fiber conductivity on a gate bias is underway and these results will also be presented.

Pinto, N. J.↗

NASA NTRS2012

Enabling Large Focal Plane Arrays through Mosaic Hybridization

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Miller, Timothy M.↗

NASA NTRS2012

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Jhabvala, Murzy↗

NASA NTRS2012

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, TImothy M.↗

NASA NTRS2012

Process for Patterning Indium for Bump Bonding

An innovation was created for the Cosmology Large Angular Scale Surveyor for integration of low-temperature detector chips with a silicon backshort and a silicon photonic choke through flipchip bonding. Indium bumps are typically patterned using liftoff processes, which require thick resist. In some applications, it is necessary to locate the bumps close to high-aspect-ratio structures such as wafer through-holes. In those cases, liftoff processes are challenging, and require complicated and time-consuming spray coating technology if the high-aspect-ratio structures are delineated prior to the indium bump process. Alternatively, processing the indium bumps first is limited by compatibility of the indium with subsequent processing. The present invention allows for locating bumps arbitrarily close to multiple-level high-aspect-ratio structures, and for indium bumps to be formed without liftoff resist. The process uses the poor step coverage of indium deposited on a silicon wafer that has been previously etched to delineate the location of the indium bumps. The silicon pattern can be processed through standard lithography prior to adding the high-aspect-ratio structures. Typically, high-aspectratio structures require a thick resist layer so this layer can easily cover the silicon topography. For multiple levels of topography, the silicon can be easily conformally coated through standard processes. A blanket layer of indium is then deposited onto the full wafer; bump bonding only occurs at the high points of the topography.

Denis, Kevin↗

NASA NTRS2012

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

Miller, Timothy M.↗