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At least 487 records · Page 27

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DOE OSTI2023

A high-resolution clock phase shifter circuitry for ALTIROC

Abstract A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

Instruments & Instrumentation↗

DOE OSTI2023

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Abstract Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

Instruments & Instrumentation↗

DOE OSTI2024

First test results of the HGCAL concentrator ASICs: ECON-T and ECON-D

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. Here, we report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy using test results from the ECON-T-P1 full-functionality prototype.

47 OTHER INSTRUMENTATION↗

DOE OSTI2024

The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

We report a very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2024

Performance evaluation of an RFSoC operating in a 1.25 Tesla magnetic field

Here, the Belle II experiment at the SuperKEKB collider is preparing for an upgrade after 2027–2028 to handle higher luminosity and increased background rates. A Radio Frequency System-on-Chip (RFSoC) has been identified as a potential candidate for a common front-end upgrade for subsystems requiring high-speed waveform digitization. The RFSoC's ADC and DAC channels were tested across various magnetic field strengths and a few different field orientations. Power consumption and boot memory functionality were also assessed. Results indicate stable operation with negligible performance degradation, suggesting the RFSoC's viability for high-speed digitization tasks in high magnetic field environments.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗

DOE OSTI2020

1.3-µm passively mode-locked quantum dot lasers epitaxially grown on silicon: gain properties and optical feedback stabilization

Abstract This work reports on an investigation of the optical feedback in an InAs/InGaAs passively mode-locked quantum dot (QD) laser epitaxially grown on silicon. Under the stably-resonant optical feedback condition, experiments demonstrate that the radio-frequency linewidth is narrowed whatever the bias voltage applied on the saturable absorber (SA) is; on the other hand, the effective linewidth enhancement factor of the device increases with the reverse bias voltage on the SA, hence it is observed that such an increase influences the mode-locking dynamic and the stability of device under optical feedback. This work gives insights for stabilizing epitaxial QD mode-locked lasers on silicon which is meaningful for their applications in future large-scale silicon electronic and photonic applications requiring low power consumption as well as for high-speed photonic analog-to-digital conversion, intrachip/interchip optical clock distribution and recovery.

Dong, Bozhang (ORCID:0000000158266723)↗

DOE OSTI2022

Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml

In this paper, we investigate how field programmable gate arrays can serve as hardware accelerators for real-time semantic segmentation tasks relevant for autonomous driving. Considering compressed versions of the ENet convolutional neural network architecture, we demonstrate a fully-on-chip deployment with a latency of 4.9 ms per image, using less than 30% of the available resources on a Xilinx ZCU102 evaluation board. The latency is reduced to 3 ms per image when increasing the batch size to ten, corresponding to the use case where the autonomous vehicle receives inputs from multiple cameras simultaneously. We show, through aggressive filter reduction and heterogeneous quantization-aware training, and an optimized implementation of convolutional layers, that the power consumption and resource utilization can be significantly reduced while maintaining accuracy on the Cityscapes dataset.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

Digital coded exposure formation of frames from event-based imagery

Abstract Event-driven neuromorphic imagers have a number of attractive properties including low-power consumption, high dynamic range, the ability to detect fast events, low memory consumption and low band-width requirements. One of the biggest challenges with using event-driven imagery is that the field of event data processing is still embryonic. In contrast, decades worth of effort have been invested in the analysis of frame-based imagery. Hybrid approaches for applying established frame-based analysis techniques to event-driven imagery have been studied since event-driven imagers came into existence. However, the process for forming frames from event-driven imagery has not been studied in detail. This work presents a principled digital coded exposure approach for forming frames from event-driven imagery that is inspired by the physics exploited in a conventional camera featuring a shutter. The technique described in this work provides a fundamental tool for understanding the temporal information content that contributes to the formation of a frame from event-driven imagery data. Event-driven imagery allows for the application of arbitrary virtual digital shutter functions to form the final frame on a pixel-by-pixel basis. The proposed approach allows for the careful control of the spatio-temporal information that is captured in the frame. Furthermore, unlike a conventional physical camera, event-driven imagery can be formed into any variety of possible frames in post-processing after the data is captured. Furthermore, unlike a conventional physical camera, coded-exposure virtual shutter functions can assume arbitrary values including positive, negative, real, and complex values. The coded exposure approach also enables the ability to perform applications of industrial interest such as digital stroboscopy without any additional hardware. The ability to form frames from event-driven imagery in a principled manner opens up new possibilities in the ability to use conventional frame-based image processing techniques on event-driven imagery.

47 OTHER INSTRUMENTATION↗

DOE OSTI2021

Tuning Dzyaloshinskii-Moriya interactions in magnetic bilayers with a ferroelectric substrate

Our group performed systematic first-principles calculations to explore the possibility of manipulating Dzyaloshinskii-Moriya interactions (DMIs) in heavy metal/ferromagnetic metal bilayers with ferroelectric (FE) polarization of a PbTiO 3 (PTO) substrate. Significantly, both the sign and magnitude of the DMI can be tailored by the FE polarization reversal in PTO. Moreover, the DMIs of Ir/Co/PTO and Ir/Fe/PTO can achieve large values (|d| > 10 meV) under the influence of an upward electric polarization of PTO. Our findings provided useful strategies for enhancing and tailoring DMIs in complex heterostructures and paved the way for the development of DMI-based devices with ultralow power consumption.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2025

Memristive linear algebra

The advent of memristive devices offers a promising avenue for efficient and scalable analog computing, particularly for linear algebra operations essential in various scientific and engineering applications. This paper investigates the potential of memristive crossbars in implementing matrix inversion algorithms. We explore both static and dynamic approaches, emphasizing the advantages of analog and in-memory computing for matrix operations beyond multiplication. In particular, we demonstrate that the electrical properties of memristive crossbars uniquely suit them for the evolution of a family of matrix exponentials, which can be exploited for the efficient computation of matrix inverses and online solutions for linear problems. Our results demonstrate that memristive arrays can reduce computational complexity. We also study power consumption and show a tradeoff between precision and energy. Furthermore, we address the challenges of device variability, precision, and scalability, providing insights into the practical implementation of these algorithms.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Magnetic structure determination of multiple phases in the multiferroic candidate GdCrO 3

Due to their potential applications in low-power consumption and/or multistate memory devices, multiferroic materials have attracted a lot of attention in the condensed matter community. As part of the effort to identify new multiferroic compounds, perovskite-based GdCrO 3 was studied in both bulk and thin film samples. A strong enhancement of the capacitance in a field suggested ferroelectric behaviour but significant leakage and no well developed P–E hysteresis loops were observed. Measurements clearly indicate the existence of a polar phase but only below 2 K (likely connected to Gd ordering). Here the determination of the magnetic structure through neutron diffraction collected on an isotopic 160 GdCrO 3 sample at the WISH diffractometer at ISIS is reported. The presence of three successive magnetic phases as a function of temperature (commensurate, spin re-orientation and incommensurate phases once the Gd order), previously only seen by magnetization, is confirmed. Using the most recent guidelines for reporting the determined structures, we highlight the benefits of using such nomenclature for discussing physical properties and consider possible mechanisms and couplings that led this seemingly rather isotropic system to display the complex structures observed.

incommensurate magnetic structure↗

DOE OSTI2022

Wavelength Scaling of Widely-Tunable Terahertz Quantum-Cascade Metasurface Lasers

Terahertz (THz) external-cavity lasers based on quantum-cascade (QC) metasurfaces are emerging as widely-tunable, single-mode sources with the potential to cover the 1--6 THz range in discrete bands with milliwatt-level output power. By operating on an ultra-short cavity with a length on the order of the wavelength, the QC vertical-external-cavity surface-emitting-laser (VECSEL) architecture enables continuous, broadband tuning while producing high quality beam patterns and scalable power output. The methods and challenges for designing the metasurface at different frequencies are discussed. As the QC-VECSEL is scaled below 2 THz, the primary challenges are reduced gain from the QC active region, increased metasurface quality factor and its effect on tunable bandwidth, and larger power consumption due to a correspondingly scaled metasurface area. At frequencies above 4.5 THz, challenges arise from a reduced metasurface quality factor and the excess absorption that occurs from proximity to the Reststrahlen band. The results of four different devices — with center frequencies 1.8 THz, 2.8 THz, 3.5 THz, and 4.5 THz — are reported. Each device demonstrated at least 200 GHz of continuous single-mode tuning, with the largest being 650 GHz around 3.5 THz. The limitations of the tuning range are well modeled by a Fabry-Pérot cavity which accounts for the reflection phase of the metasurface and the effect of the metasurface quality factor on laser threshold. Lastly, the effect of different output couplers on device performance is studied, demonstrating a significant trade-off between the slope efficiency and tuning bandwidth.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

An Open Source Perovskite Solar Cell Curve Tracer

When developing systems for perovskite solar cells (PSCs), it is important to have a testing platform that closely resembles your deployed systems. While developing a 1 U CubeSat, the Big Red Sat-1 at the University of Nebraska-Lincoln, we found a lack of passive curve tracing instrumentation, which we needed for our mission. To that end, we developed a benchtop passive curve tracer that leverages the Ossila Solar Simulator as an AM1.5 light source. This device utilizes a ladder of switched resistors and a precision voltage and current measurement to achieve the curve tracing. It also integrates a common-anode multiplexer to switch through multipixel PSCs. Finally, the solar cell holder is separate from the main measurement system, so various substrates sizes and pixel counts can be supported. This system is tested using various PSCs. It has been open sourced to enable reuse in future systems that may benefit from the lower power consumption and flight heritage.

14 SOLAR ENERGY↗

DOE OSTI2023

A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm 2 Area Efficiency

Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal cancellation in full-duplex, and for isolation from reflections in signal repeaters. However, programmable broadband RF delay has been limited to ones of ns due to challenges in miniaturization with low loss and low power consumption. In this work, we present a 0.2–2 GHz digitally programmable RF delay element based on a time-interleaved multistage switched-capacitor (TIMS-SC) approach. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. Further, the delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55–448.6 ns programmable delay range with < 0.12% delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm 2 area efficiency. Through the proposed approach, the device shows minimal delay change across a -40 °C to 85 °C temperature range and < 0.25 dB gain variation across delay settings. The device achieves 26 dB gain, 7.4 dB noise figure, and consumes 74 mW from a 1 V supply with an active area of 1.36 mm 2 .

42 ENGINEERING↗