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At least 487 records · Page 27

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NASA NTRS1986

ERS-1 SAR data processing

To take full advantage of the synthetic aperature radar (SAR) to be flown on board the European Space Agency's Remote Sensing Satellite (ERS-1) (1989) and the Canadian Radarsat (1990), the implementation of a receiving station in Alaska is being studied to gather and process SAR data pertaining in particular to regions within the station's range of reception. The current SAR data processing requirement is estimated to be on the order of 5 minutes per day. The Interim Digital Sar Processor (IDP) which was under continual development through Seasat (1978) and SIR-B (1984) can process slightly more than 2 minutes of ERS-1 data per day. On the other hand, the Advanced Digital SAR Processore (ADSP), currently under development for the Shuttle Imaging Radar C (SIR-C, 1988) and the Venus Radar Mapper, (VMR, 1988), is capable of processing ERS-1 SAR data at a real time rate. To better suit the anticipated ERS-1 SAR data processing requirement, both a modified IDP and an ADSP derivative are being examined. For the modified IDP, a pipelined architecture is proposed for the mini-computer plus array processor arrangement to improve throughout. For the ADSP derivative, a simplified version is proposed to enhance ease of implementation and maintainability while maintaing real time throughput rates. These processing systems are discussed and evaluated.

Leung, K.↗

NASA NTRS1987

Design and initial application of the extended aircraft interrogation and display system: Multiprocessing ground support equipment for digital flight systems

A pipelined, multiprocessor, general-purpose ground support equipment for digital flight systems has been developed and placed in service at the NASA Ames Research Center's Dryden Flight Research Facility. The design is an outgrowth of the earlier aircraft interrogation and display system (AIDS) used in support of several research projects to provide engineering-units display of internal control system parameters during development and qualification testing activities. The new system, incorporating multiple 16-bit processors, is called extended AIDS (XAIDS) and is now supporting the X-29A forward-swept-wing aircraft project. This report describes the design and mechanization of XAIDS and shows the steps whereby a typical user may take advantage of its high throughput and flexible features.

Glover, Richard D.↗

NASA NTRS1987

A VLSI architecture of a binary updown counter

A pipeline binary updown counter with many bits is developed which can be used in a variety of applications. One such application includes the design of a digital correlator for very long baseline interferometry (VLBI). The advantage of the presently conceived approach over the previous techniques is that the number of logic operations involved in the design of the binary updown counter can be reduced substantially. The architecture design using these methods is regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Reed, I. S.↗

NASA NTRS1987

Wind shear and turbulence simulation

The aviation community is increasing its reliance on flight simulators. This is true both in pilot training and in research and development. In moving research concepts through the development pipeline, there is a sequence of events which take place: analysis, ground based simulation, inflight simulation, and flight testing. Increasing fidelity as progress toward the flight testing arena is accompanied by increasing cost. The question that seems to be posed in relation to the meteorological aspects of flight simulation is, How much fidelity is enough and can it be quantified. As a part of the Langley Simulation Technology Program, there are three principal areas of focus, one being improved simulation of weather hazards. A close liaison with the JAWS project was established because of the Langley Simulation Technology interests regarding reliable simulation of severe convective weather phenomena and their impact on aviation systems. Simulation offers the only feasible approach for examining the utility of new technology and new procedures for coping with severe convective weather phenomena such as wind shear. These simulation concepts are discussed in detail.

Bowles, Roland L.↗

NASA NTRS1987

Onboard multichannel demultiplexer/demodulator

An investigation performed for NASA LeRC by COMSAT Labs, of a digitally implemented on-board demultiplexer/demodulator able to process a mix of uplink carriers of differing bandwidths and center frequencies and programmable in orbit to accommodate variations in traffic flow is reported. The processor accepts high speed samples of the signal carried in a wideband satellite transponder channel, processes these as a composite to determine the signal spectrum, filters the result into individual channels that carry modulated carriers and demodulate these to recover their digital baseband content. The processor is implemented by using forward and inverse pipeline Fast Fourier Transformation techniques. The recovered carriers are then demodulated using a single digitally implemented demodulator that processes all of the modulated carriers. The effort has determined the feasibility of the concept with multiple TDMA carriers, identified critical path technologies, and assessed the potential of developing these technologies to a level capable of supporting a practical, cost effective on-board implementation. The result is a flexible, high speed, digitally implemented Fast Fourier Transform (FFT) bulk demultiplexer/demodulator.

Campanella, S. Joseph↗

NASA NTRS1985

Supercomputing on massively parallel bit-serial architectures

Research on the Goodyear Massively Parallel Processor (MPP) suggests that high-level parallel languages are practical and can be designed with powerful new semantics that allow algorithms to be efficiently mapped to the real machines. For the MPP these semantics include parallel/associative array selection for both dense and sparse matrices, variable precision arithmetic to trade accuracy for speed, micro-pipelined train broadcast, and conditional branching at the processing element (PE) control unit level. The preliminary design of a FORTRAN-like parallel language for the MPP has been completed and is being used to write programs to perform sparse matrix array selection, min/max search, matrix multiplication, Gaussian elimination on single bit arrays and other generic algorithms. A description is given of the MPP design. Features of the system and its operation are illustrated in the form of charts and diagrams.

Iobst, Ken↗

NASA NTRS1986

Two-dimensional nonsteady viscous flow simulation on the Navier-Stokes computer miniNode

The needs of large-scale scientific computation are outpacing the growth in performance of mainframe supercomputers. In particular, problems in fluid mechanics involving complex flow simulations require far more speed and capacity than that provided by current and proposed Class VI supercomputers. To address this concern, the Navier-Stokes Computer (NSC) was developed. The NSC is a parallel-processing machine, comprised of individual Nodes, each comparable in performance to current supercomputers. The global architecture is that of a hypercube, and a 128-Node NSC has been designed. New architectural features, such as a reconfigurable many-function ALU pipeline and a multifunction memory-ALU switch, have provided the capability to efficiently implement a wide range of algorithms. Efficient algorithms typically involve numerically intensive tasks, which often include conditional operations. These operations may be efficiently implemented on the NSC without, in general, sacrificing vector-processing speed. To illustrate the architecture, programming, and several of the capabilities of the NSC, the simulation of two-dimensional, nonsteady viscous flows on a prototype Node, called the miniNode, is presented.

Nosenchuck, Daniel M.↗

NASA NTRS1986

Case histories involving fatigue and fracture mechanics; Proceedings of the Symposium, Charleston, SC, Mar. 21, 22, 1985

Papers are presented on cracking at nozzle corners in the nuclear pressure vessel industry, applied fracture mechanics for assessing defect significance in a crude oil pipeline, failure analysis of a large wind-tunnel compressor blade, analysis of a compressor-wheel failure, and preventing fracture by inspection and analysis. Consideration is also given to the fatigue crack growth predictions of welded aircraft structures containing flaws in the residual stress field, the fatigue and fracture mechanics analysis of a compression loaded aircraft structure, fracture of an aircraft horizontal stabilizer, fatigue life analysis of fuel tank skins under combined loads, and aircraft structural maintenance recommendations based on fracture mechanics analysis. Additional papers discuss an analysis of two metal-forming die failures, an analysis of a failed saw arbor, and the role of fracture mechanics in assessing the effect on fatigue life of design changes in welded fabrications.

Hudson, C. Michael↗

NASA NTRS1988

VLSI Architecture Of A Binary Up/Down Counter

Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.

Hsu, In-Shek↗

NASA NTRS1988

Single-Chip VLSI Reed-Solomon Decoder

Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.

Shao, Howard M.↗

NASA NTRS1988

Real time thermal imaging of high temperature semiconductor melts

A real time thermal imaging system with temperature resolution better than + or - 1 C and spatial resolution of better than 0.5 mm was developed and applied to the analysis of melt surface thermal field distributions in both Czochralski and liquid encapsulated Czochralski (LEC) growth configurations. The melt is viewed in near normal incidence by a high resolution charge coupled device camera to which is attached a very narrow bandpass filter. The resulting image is digitized and processed using a pipelined pixel processor operating at an effective 40 million operations per second thus permitting real time high frequency spatial and temporal filtering of the high temperature scene. A multi-pixel averaging algorithm was developed which permits localized, low noise sensing of temperature variations at any location in the hot zone as a function of time. This signial is used to implement initial elements of a feedforward growth control scheme which is aimed at reducing disturbances to the melt caused by the batch nature of the growth process. The effect of magnetic melt stabilization on radial melt temperature distributions was measured using this technique. Problems associated with residual internal reflections and non-optimized path geometry are discussed.

Wargo, Michael J.↗

NASA NTRS1988

Nanosequencer digital logic controller

A digital logic controller provides instruction execution times on the order of 50 nanoseconds and employing read-only memory outputting instructions to a pipeline register, a portion of each instruction providing a status-select control signal and address signals for controlling selection of the next instruction from the read-only memory.

Charles R Lahmeyer↗

NASA NTRS1987

Sensing and perception research for space telerobotics at JPL

PIFLEX is a pipelined-image processor that can perform elaborate computations whose exact nature is not fixed in the hardware, and that can handle multiple images. A wire-wrapped prototype PIFEX module has been produced and debugged, using a version of the convolver composed of three custom VLSI chips (plus the line buffers). A printed circuit layout is being designed for use with a single-chip convolver, leading to production of a PIFEX with about 120 modules. A high-level language for programming PIFEX has been designed, and a compiler will be written for it. The camera calibration software has been completed and tested. Two more terms in the camera model, for lens distortion, probably will be added later. The acquisition and tracking system has been designed and most of it has been coded in Pascal for the MicroVAX-II. The feature tracker, motion stereo module and stereo matcher have executed successfully. The model matcher is still under development, and coding has begun on the tracking initializer. The object tracker was running on a different computer from the VAX, and preliminary runs on real images have been performed there. Once all modules are working, optimization and integration will begin. Finally, when a sufficiently large PIFEX is available, appropriate parts of acquisition and tracking, including much of the feature tracker, will be programmed into PIFEX, thus increasing the speed and robustness of the system.

Gennery, Donald B.↗

NASA NTRS1989

General-Purpose Electronic System Tests Aircraft

Versatile digital equipment supports research, development, and maintenance. Extended aircraft interrogation and display system is general-purpose assembly of digital electronic equipment on ground for testing of digital electronic systems on advanced aircraft. Many advanced features, including multiple 16-bit microprocessors, pipeline data-flow architecture, advanced operating system, and resident software-development tools. Basic collection of software includes program for handling many types of data and for displays in various formats. User easily extends basic software library. Hardware and software interfaces to subsystems provided by user designed for flexibility in configuration to meet user's requirements.

Glover, Richard D.↗

NASA NTRS1988

A hardware implementation of a relaxation algorithm to segment images

Relaxation labelling is a mathematical technique frequently applied in image processing algorithms. In particular, it is extensively used for the purpose of segmenting images. The paper presents a hardware implementation of a segmentation algorithm, for images consisting of two regions, based on relaxation labelling. The algorithm determines, for each pixel, the probability that it should be labelled as belonging to a particular region, for all regions in the image. The label probabilities (labellings) of every pixel are iteratively updated, based on those of the pixel's neighbors, until they converge. The pixel is then assigned to the region correspondent to the maximum label probability. The system consists of a control unit and of a pipeline of segmentation stages. Each segmentation stage emulates in the hardware an iteration of the relaxation algorithm. The design of the segmentation stage is based on commercially available digital signal processing integrated circuits. Multiple iterations are accomplished by stringing stages together or by looping the output of a stage, or string of stages, to its input. The system interfaces with a generic host computer. Given the modularity of the architecture, performance can be enhanced by merely adding segmentation stages.

Loda, Antonio G.↗

NASA NTRS1988

The Alaska SAR processor

The Alaska SAR processor was designed to process over 200 100 km x 100 km (Seasat like) frames per day from the raw SAR data, at a ground resolution of 30 m x 30 m from ERS-1, J-ERS-1, and Radarsat. The near real time processor is a set of custom hardware modules operating in a pipelined architecture, controlled by a general purpose computer. Input to the processor is provided from a high density digital cassette recording of the raw data stream as received by the ground station. A two pass processing is performed. During the first pass clutter-lock and auto-focus measurements are made. The second pass uses the results to accomplish final image formation which is recorded on a high density digital cassette. The processing algorithm uses fast correlation techniques for range and azimuth compression. Radiometric compensation, interpolation and deskewing is also performed by the processor. The standard product of the ASP is a high resolution four-look image, with a low resolution (100 to 200 m) many look image provided simultaneously.

Carande, R. E.↗

NASA NTRS1988

Presentation planning using an integrated knowledge base

A description is given of user interface research aimed at bringing together multiple input and output modes in a way that handles mixed mode input (commands, menus, forms, natural language), interacts with a diverse collection of underlying software utilities in a uniform way, and presents the results through a combination of output modes including natural language text, maps, charts and graphs. The system, Integrated Interfaces, derives much of its ability to interact uniformly with the user and the underlying services and to build its presentations, from the information present in a central knowledge base. This knowledge base integrates models of the application domain (Navy ships in the Pacific region, in the current demonstration version); the structure of visual displays and their graphical features; the underlying services (data bases and expert systems); and interface functions. The emphasis is on a presentation planner that uses the knowledge base to produce multi-modal output. There has been a flurry of recent work in user interface management systems. (Several recent examples are listed in the references). Existing work is characterized by an attempt to relieve the software designer of the burden of handcrafting an interface for each application. The work has generally focused on intelligently handling input. This paper deals with the other end of the pipeline - presentations.

Arens, Yigal↗

NASA NTRS1989

Model evaluation, recommendation and prioritizing of future work for the manipulator emulator testbed

The Manipulator Emulator Testbed (MET) is to provide a facility capable of hosting the simulation of various manipulator configurations to support concept studies, evaluation, and other engineering development activities. Specifically, the testbed is intended to support development of the Space Station Remote Manipulator System (SSRMS) and related systems. The objective of this study is to evaluate the math models developed for the MET simulation of a manipulator's rigid body dynamics and the servo systems for each of the driven manipulator joints. Specifically, the math models are examined with regard to their amenability to pipeline and parallel processing. Based on this evaluation and the project objectives, a set of prioritized recommendations are offered for future work.

Kelly, Frederick A.↗