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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 487 records · Page 27
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Advanced sensible heat solar receiver for space power

NASA Lewis, through in-house efforts, has begun a study to generate a conceptual design of a sensible heat solar receiver and to determine the feasibility of such a system for space power applications. The sensible heat solar receiver generated in this study uses pure lithium as the thermal storage medium and was designed for a 7 kWe Brayton (PCS) operating at 1100 K. The receiver consists of two stages interconnected via temperature sensing variable conductance sodium heat pipes. The lithium is contained within a niobium vessel and the outer shell of the receiver is constructed of third generation rigid, fibrous ceramic insulation material. Reradiation losses are controlled with niobium and aluminum shields. By nature of design, the sensible heat receiver generated in this study is comparable in both size and mass to a latent heat system of similar thermal capacitance. The heat receiver design and thermal analysis was conducted through the combined use of PATRAN, SINDA, TRASYS, and NASTRAN software packages.

Bennett, Timothy J.↗
NASA NTRS1988

Advanced sensible heat solar receiver for space power

NASA Lewis, through in-house efforts, has begun a study to generate a conceptual design of a sensible heat solar receiver and to determine the feasibility of such a system for space power applications. The sensible heat solar receiver generated in this study uses pure lithium as the thermal storage medium and was designed for a 7 kWe Brayton (PCS) operating at 1100 K. The receiver consists of two stages interconnected via temperature sensing variable conductance sodium heat pipes. The lithium is contained within a niobium vessel and the outer shell of the receiver is constructed of third generation rigid, fibrous ceramic insulation material. Reradiation losses are controlled with niobium and aluminum shields. By nature of design, the sensible heat receiver generated in this study is comparable in both size and mass to a latent heat system of similar thermal capacitance. The heat receiver design and thermal analysis were conducted through the combined use of PATRAN, SINDA, TRASYS, and NASTRAN software packages.

Bennett, Timothy J.↗
NASA NTRS1989

The role of the host in a cooperating mainframe and workstation environment, volumes 1 and 2

In recent years, advancements made in computer systems have prompted a move from centralized computing based on timesharing a large mainframe computer to distributed computing based on a connected set of engineering workstations. A major factor in this advancement is the increased performance and lower cost of engineering workstations. The shift to distributed computing from centralized computing has led to challenges associated with the residency of application programs within the system. In a combined system of multiple engineering workstations attached to a mainframe host, the question arises as to how does a system designer assign applications between the larger mainframe host and the smaller, yet powerful, workstation. The concepts related to real time data processing are analyzed and systems are displayed which use a host mainframe and a number of engineering workstations interconnected by a local area network. In most cases, distributed systems can be classified as having a single function or multiple functions and as executing programs in real time or nonreal time. In a system of multiple computers, the degree of autonomy of the computers is important; a system with one master control computer generally differs in reliability, performance, and complexity from a system in which all computers share the control. This research is concerned with generating general criteria principles for software residency decisions (host or workstation) for a diverse yet coupled group of users (the clustered workstations) which may need the use of a shared resource (the mainframe) to perform their functions.

Kusmanoff, Antone↗
NASA NTRS2004

Development of a Multi-bus, Multi-source Reconfigurable Stirling Radioisotope Power System Test Bed

The National Aeronautics and Space Administration (NASA) has typically used Radioisotope Thermoelectric Generators (RTG) as their source of electric power for deep space missions. A more efficient and potentially more cost effective alternative to the RTG, the high efficiency 110 watt Stirling Radioisotope Generator 110 (SRG110) is being developed by the Department of Energy (DOE), Lockheed Martin (LM), Stirling Technology Company (STC) and NASA Glenn Research Center (GRC). The SRG110 consists of two Stirling convertors (Stirling Engine and Linear Alternator) in a dual-opposed configuration, and two General Purpose Heat Source (GPHS) modules. Although Stirling convertors have been successfully operated as a power source for the utility grid and as a stand-alone portable generator, demonstration of the technology required to interconnect two Stirling convertors for a spacecraft power system has not been attempted. NASA GRC is developing a Power System Test Bed (PSTB) to evaluate the performance of a Stirling convertor in an integrated electrical power system application. This paper will describe the status of the PSTB and on-going activities pertaining to the PSTB in the NASA Thermal-Energy Conversion Branch of the Power and On-Board Propulsion Technology Division.

Coleman, Anthony S.↗
NASA NTRS2021

Systems Engineering and Assurance Modeling (SEAM): A Web-Based Solution for Integrated Mission Assurance

We present an overview of the Systems Engineering and Assurance Modeling (SEAM) platform, a web-browser-based tool which is designed to help engineers evaluate the radiation vulnerabilities and develop an assurance approach for electronic parts in space systems. The SEAM framework consists of three interconnected modeling tools, a SysML compatible system description tool, a Goal Structuring Notation (GSN) visual argument tool, and Bayesian Net and Fault Tree extraction and export tools. The SysML and GSN sections also have a coverage check application that ensures that every radiation fault identified on the SysML side is also addressed in the assurance case in GSN. The SEAM platform works on space systems of any degree of radiation hardness but is especially helpful for assessing radiation performance in systems with commercial-off-the-shelf (COTS) electronic components.

SEAM↗
DOE OSTI2025

Smart Contracts for Power Grid Applications Using the Advanced DLT Cyber Grid Guard Testbed

In this study is presented two power system applications with distributed ledger technology (DLT) and smart contracts (SC) that were assessed in a Cyber-Grid-Guard System (CGGS) advanced testbed, with protective relays, power meters, communication devices, DLT devices, synchronized time source, clock displays and real time simulator. This CGGS testbed was set in the Advanced Protection Lab, 252 lab space of the Grid Research Integration and Deployment Center (GRID- C), at Oak Ridge National Laboratory. In power grids, customer-owned distributed energy resources (DERs) are more frequent than in the past, and the numbers of points of interconnection (POI) with customer-owned DERs have increased. Disruptive operation from DERs presents a risk to grid operations, and protective relays located at the POI are used to isolate out-of-tolerance or poorly behaving of DERs. Ensuring the integrity of data from the relays at the POI, and DLT could enhance the security of the power grids. The first application is a SC to define and control the allowable total power factor (TPF) of the DER (wind farm) output, and the terms of the SC are implemented using DLT with a CGGS for a customer-owned DER. The TPF SC was implemented by the CGGS using DLT. The experimental model was performed with a real-time simulator using a CGGS and relay in-the-loop. The data collected from the CGGS were used to execute the TPF SC. The TPF limits were between +0.9 and +1.0, and the breakers’ operation in the POI was controlled by the relay using the SC. The events were collected from the real-time simulator, CGGS, and SEL 700GT relay to validate a successful application of the TPF SC using DLT. The second application is a SC to measure and control the allowable voltage service limits (VSL) by the CGGS using DLT. The tests were performed by using a real-time simulator, CGGS and relay in-the-loop. The data was collected from the CGGS that executed the SC. The main constraints were defined based on ANSI C84.1 service voltage limits, and the operation of the breakers in the POI. The events were collected from the CGGS, and SEL 700GT relay to assess a successful operation of the VSL SC using DLT.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1989

NASA ground communications

As part of the Communications Requirements and Constraints, NASA's two major Ground Data Networks were briefly described. The NASA Communication Network, called NASCOM, is the worldwide operational telecommunications system which interconnects as the tracking and telemetry acquisition sites, launch areas, mission and project control centers, data capture facilities, and network control centers in support of space flight. For the Space Station era, NASCOM plans are set for higher data rate service utilizing data packet switched technology. Increased use of fiber optics is expected in a much more diverse network topology. The second major ground network, the Program Support Communications Network (PSCN), interconnects all NASA Centers and NASA contractor locations for intercenter non-operation communications. The primary functions are to transport voice, video, data and facsimile information for intercenter coordination, and to provide user access to space science and applications data bases. For the Space Station era, PSCN plans address the significant increase in forecast requirements for science data distribution and access to the Numerical Aerodynamics Simulator, and increased use of the Video Teleconference System.

Roeder, John↗
NASA NTRS1989

Simulation studies using multibody dynamics code DART

DART is a multibody dynamics code developed by Photon Research Associates for the Air Force Astronautics Laboratory (AFAL). The code is intended primarily to simulate the dynamics of large space structures, particularly during the deployment phase of their missions. DART integrates nonlinear equations of motion numerically. The number of bodies in the system being simulated is arbitrary. The bodies' interconnection joints can have an arbitrary number of degrees of freedom between 0 and 6. Motions across the joints can be large. Provision for simulating on-board control systems is provided. Conservation of energy and momentum, when applicable, are used to evaluate DART's performance. After a brief description of DART, studies made to test the program prior to its delivery to AFAL are described. The first is a large angle reorientating of a flexible spacecraft consisting of a rigid central hub and four flexible booms. Reorientation was accomplished by a single-cycle sine wave shape torque input. In the second study, an appendage, mounted on a spacecraft, was slewed through a large angle. Four closed-loop control systems provided control of this appendage and of the spacecraft's attitude. The third study simulated the deployment of the rim of a bicycle wheel configuration large space structure. This system contained 18 bodies. An interesting and unexpected feature of the dynamics was a pulsing phenomena experienced by the stays whole playout was used to control the deployment. A short description of the current status of DART is given.

Keat, James E.↗
DOE OSTI2026

Binder-Free Graphite Anodes for Next-Generation High-Performance Lithium-Ion Batteries

High-energy density anodes are crucial for next-generation lithium-ion batteries (LIBs) particularly for electric vehicle (EV) applications. Sluggish lithium-diffusion kinetics coupled with conventional anode fabrication processes containing polymeric binders hinder fast-charging capabilities and high-energy density of graphite. Herein, we introduce a binder-free graphite anode fabrication strategy using the electrospinning technique that contains ~2.41% carbon nanotubes (CNTs). Our strategy relies on the formation of an interconnecting conductive CNT network coupled with an ultrathin N-doped carbon coating on graphite particles from sacrificial binders. This combination enhances both structural integrity and electrical conductivity and, in turn, improves fast-charging capabilities and high energy density of LIBs. The binder-free graphite anode achieves ~335.0 mAh g–1 capacity at C/3 rate over 400 cycles with capacity retention of >95% and average Coulombic efficiencies >99.95%. These promising results suggest that the binder-free anode fabrication with a multifunctional design approach could elevate the energy-density limits of the graphite anodes, solving high-energy density requirements of EVs, and potentially provides a path forward for the development of economically feasible energy storage systems for various applications.

Ozcan, Muca [ORNL] (ORCID:0000000320020474)↗
NASA NTRS1982

Application of In Situ Fiberization for fabrication of improved strain isolation pads and graphite epoxy composites

The feasibility of applying the in situ fiberization process to the fabrication of strain isolation pads (SIP) for the Space Shuttle and to the fabrication of graphite-epoxy composites was evaluated. The ISF process involves the formation of interconnected polymer fiber networks by agitation of dilute polymer solutions under controlled conditions. High temperature polymers suitable for SIP use were fiberized and a successful fiberization of polychloro trifluoroethylene, a relatively high melting polymer, was achieved. Attempts to fiberize polymers with greater thermal stability were unsuccessful, apparently due to characteristics caused by the presence of aromaticity in the backbone of such materials. Graphite-epoxy composites were fabricated by interconnecting two dimensional arrays of graphite fiber with polypropylene IS fibers with subsequent epoxy resin impregnation. Mechanical property tests were performed on laminated panels of this material to evaluate intralaminar and interlaminar shear strength, and thus fracture toughness. Test results were generally unpromising.

Rosser, R. W.↗
DOE OSTI2025

Chemical Redox Agent-Driven Noncorrosive Formation of Nanoporous Mg Structures for Advanced Hydrogen Storage

Light metal-based nanomaterials are widely used for energy storage due to their high energy density and surface-to-volume ratio. However, their high reactivity is paradoxically both the source of advantageous properties and a hurdle to the fabrication of stable nanostructures. Here, in this study, we demonstrate the formation of nanoporous Mg via chemical redox agent-driven dealloying, which ensures minimized surface passivation and results in fine nanostructures with <50 nm of interconnected metallic ligament despite the labile chemical properties of Mg. The thin passivation layer protects the metallic ligaments from severe coarsening by suppressing surface diffusion. The hydrogen storage performance of nanoporous Mg is investigated as an exemplar for energy applications, and the hydrogen ab/desorption kinetics is substantially enhanced compared to other nano-Mg with similar dimensions. Mesoscale simulations highlight the significance of the bicontinuous structure compared to the particle-like counterpart. This work offers valuable insights into the unexplored realm of reactive metal-based nanoporous structures, highlighting their potential for sustainable energy storage and carrier media.

08 HYDROGEN↗
NASA NTRS1979

Wraparound-contact solar cells

Positive and negative electrical contacts are on back surface of wraparound-contact solar cell. With both terminals on nonilluminated side, cells can be connected back-to-back, and interconnection of many cells can be automated by using printed-circuit techniques. Cells are made by screen-printing layer of dielectric around edge of cell and extending top contact over dielectric to back surface. Wraparound also facilitates application of transparent covers and encapsulants. Efficiencies of cells are in excess of seventeen percent.

Baraona, C. R.↗
NASA NTRS1981

A Module Experimental Process System Development Unit (MEPSDU)

Design work for a photovoltaic module, fabricated using single crystal silicon dendritic web sheet material, resulted in the identification of surface treatment to the module glass superstrate which improved module efficiencies. A final solar module environmental test, a simulated hailstone impact test, was conducted on full size module superstrates to verify that the module's tempered glass superstrate can withstand specified hailstone impacts near the corners and edges of the module. Process sequence design work on the metallization process selective, liquid dopant investigation, dry processing, and antireflective/photoresist application technique tasks, and optimum thickness for Ti/Pd are discussed. A noncontact cleaning method for raw web cleaning was identified and antireflective and photoresist coatings for the dendritic webs were selected. The design of a cell string conveyor, an interconnect feed system, rolling ultrasonic spot bonding heat, and the identification of the optimal commercially available programmable control system are also discussed. An economic analysis to assess cost goals of the process sequence is also given.

Source record↗
DOE OSTI2020

Holistic Measurement Driven Resilience: Combining Operational Fault and Failure Measurements and Fault Injection for Quantifying Fault Detection, Propagation and Impact. Final report

For HPC systems to date, application resilience to faults and failures has been accomplished by the brute- force method of checkpoint/restart, which allows an application to make forward progress in the face of system and application faults, errors, and failures independent of root cause or end result. It has remained the primary resilience mechanism because we lack a way to identify faults and anticipate consequences early enough to take meaningful mitigating action. However, checkpoint/restart implementations put a tremendous burden on system resources and on the applications themselves and is becoming less feasible at scale. Because we have not yet operated at scales at which checkpoint/restart fails to provide forward progress, despite increasing costs, vendors have had little motivation to provide the instrumentation necessary for early identification of faults and failures. However, as we move from petascale to exascale, component mean time to failure (MTTF) will render the existing techniques ineffectual and/or too expensive. Furthermore, fault recovery mechanisms such as failover and/or error correction introduce performance inconsistency. Instrumentation allowing early indication of problems and tools to enable use of such information by systems, operating systems, and applications offer an alternative, more scalable and less costly solution. In the HMDR project, we built on our experience and expertise developed and accumulated over years of research on design, monitoring, measurement, and assessment of resilient computing systems. Analysis of field data on the current and past generations of extreme-scale systems revealed several challenges that, if not addressed in increasingly larger and more complex systems, may hinder the effectiveness of future exascale computing systems. Specifically, i) file systems and interconnects in current-generation large-scale systems already operate at the margins of resiliency, including consistent performance, and may not scale to larger deployments; ii) automated, software-based failover mechanisms are frequently inadequate and can introduce wider failures, such that failures during recovery may lead to system/application failures, including system-wide outages; and iii) silent data corruption represents a critical fault mode and will require efficient detection mechanisms if next-generation applications are to take full advantage of exascale hardware. To address the above challenges, we assembled a team of world-renowned experts in resilient extreme- scale computing from the University of Illinois (Electrical and Computer Engineering, Computer Science, and NCSA), SNL, LANL, NERSC, and Cray. Our team includes representatives from centers that house many of the largest HPC resources in the world, both today and over the coming years. The team has a unique track record of research in i) system and application failure characterization based on the analysis of field data, ii) data-driven design of fault/error detection mechanisms, and iii) experimental characterization of system/application resiliency. The team includes system owners/operators who provide continuous data collection and access and ensure installation of appropriate analysis tools.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2010

High-Speed Ring Bus

The high-speed ring bus at the Jet Propulsion Laboratory (JPL) allows for future growth trends in spacecraft seen with future scientific missions. This innovation constitutes an enhancement of the 1393 bus as documented in the Institute of Electrical and Electronics Engineers (IEEE) 1393-1999 standard for a spaceborne fiber-optic data bus. It allows for high-bandwidth and time synchronization of all nodes on the ring. The JPL ring bus allows for interconnection of active units with autonomous operation and increased fault handling at high bandwidths. It minimizes the flight software interface with an intelligent physical layer design that has few states to manage as well as simplified testability. The design will soon be documented in the AS-1393 standard (Serial Hi-Rel Ring Network for Aerospace Applications). The framework is designed for "Class A" spacecraft operation and provides redundant data paths. It is based on "fault containment regions" and "redundant functional regions (RFR)" and has a method for allocating cables that completely supports the redundancy in spacecraft design, allowing for a complete RFR to fail. This design reduces the mass of the bus by incorporating both the Control Unit and the Data Unit in the same hardware. The standard uses ATM (asynchronous transfer mode) packets, standardized by ITU-T, ANSI, ETSI, and the ATM Forum. The IEEE-1393 standard uses the UNI form of the packet and provides no protection for the data portion of the cell. The JPL design adds optional formatting to this data portion. This design extends fault protection beyond that of the interconnect. This includes adding protection to the data portion that is contained within the Bus Interface Units (BIUs) and by adding to the signal interface between the Data Host and the JPL 1393 Ring Bus. Data transfer on the ring bus does not involve a master or initiator. Following bus protocol, any BIU may transmit data on the ring whenever it has data received from its host. There is no centralized arbitration or bus granting. The JPL design provides for autonomous synchronization of the nodes on the ring bus. An address-synchronous latency adjust buffer (LAB) has been designed that cannot get out of synchronization and needs no external input. Also, a priority-driven cable selection behavior has been programmed into each unit on the ring bus. This makes the bus able to connect itself up, according to a maximum redundancy priority system, without the need for computer intervention at startup. Switching around a failed or switched-off unit is also autonomous. The JPL bus provides a map of all the active units for the host computer to read and use for fault management. With regard to timing, this enhanced bus recognizes coordinated timing on a spacecraft as critical and addresses this with a single source of absolute and relative time, which is broadcast to all units on the bus with synchronization maintained to the tens of nanoseconds. Each BIU consists of up to five programmable triggers, which may be programmed for synchronization of events within the spacecraft of instrument. All JPL-formatted data transmitted on the ring bus are automatically time-stamped.

Wysocky, Terry↗
DOE OSTI2025

Wastepaper-derived porous carbon supported cobalt nanocomposites for all solid-state flexible supercapacitor

The conversion of wastepaper into high-value carbon materials has gained significant attention as a sustainable strategy for energy storage applications. Owing to its low cost, abundance, and intrinsic fibrous structure, wastepaper serves as an attractive precursor for carbon-based electrode materials. In this work, a novel electrode comprising cobalt nanoparticles and Co 3 O 4 embedded in wastepaper-derived porous carbon has been developed for use in a flexible all-solid-state asymmetric supercapacitor. The integration of cobalt nanoparticles and Co 3 O 4 introduces redox-active centres, which enhance the electrochemical activity of the carbon framework. Mean while, the interconnected porous and conductive carbon network enables rapid ion diffusion and efficient electron transport, synergistically improving the overall electrochemical performance. It delivers a high specific capacitance of 61.5 Fg -1 , a power density of 5143 W kg -1 , and an energy density of 9 Wh kg -1 at a current density of 2.5 A/ g. Furthermore, the device maintains outstanding cycling stability, retaining 82.86 % of its capacitance after 10,000 charge-discharge cycles. Practical applicability is confirmed through its ability to power

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale (V.2.0)

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. The errors resulting from these faults will propagate and generate various kinds of failures, which may result in outcomes ranging from result corruptions to catastrophic application crashes. Therefore, the resilience challenge for extreme-scale HPC systems requires coordination between various hardware and software technologies that are capable of handling a broad set of fault models at accelerated fault rates. Also, due to practical limits on power consumption in future HPC systems, they are likely to embrace innovative architectures, increasing the levels of hardware and software complexities. Therefore, the techniques that seek to improve resilience must navigate the complex trade-off space between resilience and the overheads to power consumption and performance. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods to integrate the various HPC resilience techniques into composite solutions, nor are there methods to holistically evaluate the adequacy and efficacy of such solutions in terms of their protection coverage, and their performance & power efficiency characteristics. Additionally, few implementations of current resilience solutions are portable to newer architectures and software environments that will be deployed on future systems. We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers' understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different efficiency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-efficient manner despite frequent faults, errors, and failures of various types. Version 2.0 expands the resilience design pattern classification and catalog to include self-stabilization patterns and reliability, availability and performance models for each structural pattern.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗