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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 487 records · Page 27
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Potential for integrated optical circuits in advanced aircraft with fiber optic control and monitoring systems

Fiber optic technology is expected to be used in future advanced weapons platforms as well as commercial aerospace applications. Fiber optic waveguides will be used to transmit noise free, high speed data between a multitude of computers as well as audio and video information to the flight crew. Passive optical sensors connected to control computers with optical fiber interconnects will serve both control and monitoring functions. Implementation of fiber optic technology has already begun. Both the military and NASA have several programs in place. A cooperative program, called FOCSI (Fiber Optic Control System Integration), between NASA Lewis and the NAVY to build, environmentally test and flight demonstrate sensor systems for propulsion and flight control systems is currently underway. Integrated Optical Circuits (IOC's) are also being given serious consideration for use in advanced aircraft systems. IOC's will result in miniaturization and localization of components to generate, detect optical signals and process them for use by the control computers. In some complex systems IOC's may be required to perform calculations optically if the technology is ready, replacing some of the electronic systems used today. IOC's are attractive because they will result in rugged components capable of withstanding severe environments in advanced aerospace vehicles. Manufacturing technology developed for microelectronic integrated circuits applied to IOC's will result in cost effective manufacturing. This paper reviews the current FOCSI program and describes the potential role of IOC's in FOCSI applications.

Robert Baumbick↗
DOE OSTI2021

Nitride-Oxide-Metal Heterostructure with Self-Assembled Core–Shell Nanopillar Arrays: Effect of Ordering on Magneto-Optical Properties

Magneto-optical (MO) coupling incorporates photon-induced change of magnetic polarization that can be adopted in ultrafast switching, optical isolators, mode convertors, and optical data storage components for advanced optical integrated circuits. However, integrating plasmonic, magnetic, and dielectric properties in one single material system poses challenges since one natural material can hardly possess all these functionalities. Here, co-deposition of a three-phase heterostructure composed of a durable conductive nitride matrix with embedded core–shell vertically aligned nanopillars, is demonstrated. Additionally, the unique coupling between ferromagnetic NiO core and atomically sharp plasmonic Au shell enables strong MO activity out-of-plane at room temperature. Further, a template growth process is applied, which significantly enhances the ordering of the nanopillar array. The ordered nanostructure offers two schemes of spin polarization which result in stronger antisymmetry of Kerr rotation. The presented complex hybrid metamaterial platform with strong magnetic and optical anisotropies is promising for tunable and modulated all-optical-based nanodevices.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Final Technical Report - Rapid Surface Microanalysis using a Low Temperature Plasma

This project focused on improving our current understanding and scientific knowledge in the area of plasma-surface interactions and plasma assisted material synthesis related to advanced microelectronics and nanotechnology. Current challenges include: controlling the interaction of Low Temperature Plasma (LTP) with a single layer of atoms to manufacture integrated circuits, continued miniaturization of integrated circuits, LTP processing of material surfaces and thin films to enable industrial scale fabrication of advanced microelectronics, synthesis of new materials, nanomaterials, nanotubes, and complex materials, Technology developed in this subtopic is of value to either (i) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at high resolution (micron or sub-micron resolution) rapidly (hours or days rather than years to complete a high-resolution scan of such a large surface area), or (ii) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at relatively low resolution rapidly, then apply algorithms to select spots for micron-scale imaging. Sputtering occurs when particles of a solid material are ejected from its surface by energetic particles from a plasma. While the degradation of the solid material and the subsequent deposition of the ejected material onto vulnerable surfaces are the usual subjects of sputtering studies, plasma science has yet to be combined with sputtering to create new diagnostics devices and systems. Small changes in the design of the plasma discharge device make it possible to create broad plasma beams for rapid scanning or small plasma beams to obtain the distribution of ejected elements with micron resolution. In the high-resolution use, the ion flux is extracted from the gas-discharge plasma and focused by a spherical emission surface to micron sizes onto the target specimen, providing very local sputtering and local elemental analysis. We call this “self-focusing”. The radiation from the excited and ionized sputtered atoms is recorded by a spectrometer through a window and fiberglass cable and analyzed with standard software packages used for optical glow discharge spectroscopy. Computer simulations of beam formation were used to verify and optimize the designs to be tested. A prototype was designed, constructed, and used to start experiments of beam formation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS1990

RLE progress report no. 133, 1 January - 31 December 1990

Activities of the Research Laboratory of Electronics at MIT are summarized. NASA-sponsored research in the area of synthetic aperture radar image interpretation and simulation is described. Other government-sponsored and industry-sponsored studies are also described which address the following topics: microwave and millimeter wave integrated circuits, high-speed integrated circuit interconnects, Instrument Landing System/Microwave Landing System frequency management assessment, and superconducting electronics.

Allen, Jonathan↗
NASA NTRS2009

On DESTINY Science Instrument Electrical and Electronics Subsystem Framework

Future space missions are going to require large focal planes with many sensing arrays and hundreds of millions of pixels all read out at high data rates'' . This will place unique demands on the electrical and electronics (EE) subsystem design and it will be critically important to have high technology readiness level (TRL) EE concepts ready to support such missions. One such omission is the Joint Dark Energy Mission (JDEM) charged with making precise measurements of the expansion rate of the universe to reveal vital clues about the nature of dark energy - a hypothetical form of energy that permeates all of space and tends to increase the rate of the expansion. One of three JDEM concept studies - the Dark Energy Space Telescope (DESTINY) was conducted in 2008 at the NASA's Goddard Space Flight Center (GSFC) in Greenbelt, Maryland. This paper presents the EE subsystem framework, which evolved from the DESTINY science instrument study. It describes the main challenges and implementation concepts related to the design of an EE subsystem featuring multiple focal planes populated with dozens of large arrays and millions of pixels. The focal planes are passively cooled to cryogenic temperatures (below 140 K). The sensor mosaic is controlled by a large number of Readout Integrated Circuits and Application Specific Integrated Circuits - the ROICs/ASICs in near proximity to their sensor focal planes. The ASICs, in turn, are serviced by a set of "warm" EE subsystem boxes performing Field Programmable Gate Array (FPGA) based digital signal processing (DSP) computations of complex algorithms, such as sampling-up-the-ramp algorithm (SUTR), over large volumes of fast data streams. The SUTR boxes are supported by the Instrument Control/Command and Data Handling box (ICDH Primary and Backup boxes) for lossless data compression, command and low volume telemetry handling, power conversion and for communications with the spacecraft. The paper outlines how the JDEM DESTINY concept instrument EE subsystem can be built now, a design; which is generally U.S. Government work not protected by U.S. copyright IEEEAC paper # 1429. Version 4. Updated October 19, 2009 applicable to a wide variety of missions using large focal planes with lar ge mosaics of sensors.

Kizhner, Semion↗
NASA NTRS2009

Wireless sensor platform for harsh environments

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna.

Garverick, Steven L.↗
NASA NTRS1980

Automatic inspection of silicon wafers

Laser machine scans wafers for contaminating particles which cause open circuits, short circuits, and other defects in integrated circuits and transfers good wafers to integrated circuit processing equipment. Machine is faster and more accurate than human operator using lightfield/dark field microscope.

Martin, M.↗
NASA NTRS2011

High-Voltage-Input Level Translator Using Standard CMOS

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.↗
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
NASA NTRS1976

Implementation of Large Scale Integrated (LSI) circuit design software

Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology.

Kuehlthau, R. L.↗
DOE OSTI2020

Discrete time analog front end circuit implemented in a receiver device

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

42 ENGINEERING↗
DOE OSTI2024

Internship Work Report

I worked on two projects during my summer internship at Sandia. My official title was “Intern - Mission Tech Electrical Eng./Computer Eng.- R&D Undergraduate Summer.” I worked at the central location, which is Albuquerque, New Mexico. The department you are placed in at Sandia doesn’t always correspond to the people you will be working with. For example, I only directly worked with one person from my department this summer. On one of my projects, I worked with a diverse team of engineers from many different departments. On my other project, I mainly worked with two departments, as the project had two distinct parts. As mentioned earlier, I worked on two projects during my summer at Sandia. The first project focused on a lightweight embedded controller in an advanced FPGA System-on-Chip for radar signal processing applications. The term “controller” refers to a hardware device that directs the flow of data between two entities. An FPGA is a reprogrammable integrated circuit (as opposed to an integrated circuit with one purpose). An FPGA was used on this project so in order to protype various ideas for our System-on-Chip. My role on the project was to implement designs on the fabric of the FPGA and design a state machine (written in C) for the processor. My second project was also heavily involved with embedded systems but had a different application. It focused on using a Newton-Raphson control algorithm to stabilize an inverted pendulum using a novel microcontroller. The pendulum dynamics were derived, and it was successfully simulated in MATLAB. I worked on integrating the microcontroller with the inverted pendulum machinery, and converting the Newton-Raphson control algorithm from MATLAB into C. The inverted pendulum was successfully stabilized using a simple PID controller and industry-standard microcontroller. The project is still ongoing, and the team is gearing up for more tests using the novel Newton-Raphson control algorithm and novel microcontroller

42 ENGINEERING↗
NASA NTRS2016

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

dielectric performance↗
NASA NTRS1987

General technique for the integration of MIC/MMIC'S with waveguides

A technique for packaging and integrating of a microwave integrated circuit (MIC) or monolithic microwave integrated circuit (MMIC) with a waveguide uses a printed conductive circuit pattern on a dielectric substrate to transform impedance and mode of propagation between the MIC/MMIC and the waveguide. The virtually coplanar circuit pattern lies on an equipotential surface within the waveguide and therefore makes possible single or dual polarized mode structures.

Geller, Bernard D.↗
NASA NTRS2018

System and Sensor for RFID-Enabled Information Collection

A system and sensor provides for radio frequency identification (RFID)-enabled information collection. The system includes a ring-shaped element and an antenna. The ring-shaped element includes a conductive ring and an RFID integrated circuit. The antenna is spaced apart from the ring-shaped element and defines an electrically-conductive path commensurate in size and shape to at least a portion of the conductive ring. In an alternate embodiment, the sensor system further comprises a reference ring-shaped element in a fixed relationship with respect to the antenna, with the reference ring-shaped element defining another series circuit to include an electrically-conductive reference ring and a reference RFID integrated circuit. The system may include an interrogator for energizing the ring-shaped element and receiving a data transmission from the RFID integrated circuit that has been energized for further processing by a processor.

Fink, Patrick W.↗