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At least 487 records · Page 27

All sources NASA NTRS DOE OSTI

DOE OSTI2025

Driving rapid atomic order in MnAl via low-magnitude magnetic field annealing

Application of a mild (60 mT), uniform magnetic field during short-term thermal treatment of kinetically retained, atomically disordered (paramagnetic) ε-MnAl was found to deliver a significant ~50 % increase in the formation of L1 0 atomically ordered (ferromagnetic) τ-MnAl product phase, compared to that produced by conventional (i.e., zero-field) annealing under identical thermal conditions. The magnetic field, applied in a passive closed-circuit configuration during annealing, induced significant changes in the structural, magnetic, and phase evolution of the material. Computational results based on electronic structure calculations demonstrate that the effective magnetic susceptibility of τ-MnAl is sensitive to the orientation, rather than the magnitude, of an applied magnetic field in the vicinity of the Curie temperature. The uniaxial magnetocrystalline anisotropy of the L1 0 structure is proposed to act as a filter for selective propagation of the population of τ-MnAl variants that are favorably aligned with the applied field. In this manner, crystallographic “gridlock” is alleviated that would otherwise arise from the coexistence of multiple, energetically equivalent τ-phase variants within the parent ε-phase matrix. These results confirm that static, low-magnitude magnetic field annealing is able to accelerate L1 0 atomic ordering in the MnAl system and likely can exert similar influences in relevant magnetic systems, facilitating efficient tailoring of structure-sensitive magnetic properties for the manufacture of magnetic materials.

36 MATERIALS SCIENCE↗

NASA NTRS1997

Sequence information signal processor for local and global string comparisons

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Peterson, John C.↗

NASA NTRS2008

Group-III Nitride Field Emitters

Field-emission devices (cold cathodes) having low electron affinities can be fabricated through lattice-mismatched epitaxial growth of nitrides of elements from group III of the periodic table. Field emission of electrons from solid surfaces is typically utilized in vacuum microelectronic devices, including some display devices. The present field-emission devices and the method of fabricating them were developed to satisfy needs to reduce the cost of fabricating field emitters, make them compatible with established techniques for deposition of and on silicon, and enable monolithic integration of field emitters with silicon-based driving circuitry. In fabricating a device of this type, one deposits a nitride of one or more group-III elements on a substrate of (111) silicon or other suitable material. One example of a suitable deposition process is chemical vapor deposition in a reactor that contains plasma generated by use of electron cyclotron resonance. Under properly chosen growth conditions, the large mismatch between the crystal lattices of the substrate and the nitride causes strains to accumulate in the growing nitride film, such that the associated stresses cause the film to crack. The cracks lie in planes parallel to the direction of growth, so that the growing nitride film becomes divided into microscopic growing single-crystal columns. The outer ends of the fully-grown columns can serve as field-emission tips. By virtue of their chemical compositions and crystalline structures, the columns have low work functions and high electrical conductivities, both of which are desirable for field emission of electrons. From examination of transmission electron micrographs of a prototype device, the average column width was determined to be about 100 nm and the sharpness of the tips was determined to be characterized by a dimension somewhat less than 100 nm. The areal density of the columns was found to about 5 x 10(exp 9)/sq cm . about 4 to 5 orders of magnitude greater than the areal density of tips in prior field-emission devices. The electric field necessary to turn on the emission current and the current per tip in this device are both lower than in prior field-emission devices, such that it becomes possible to achieve longer operational lifetime. Moreover, notwithstanding the lower current per tip, because of the greater areal density of tips, it becomes possible to achieve greater current density averaged over the cathode area. The thickness of the grown nitride film (equivalently, the length of the columns) could lie between about 0.5 microns and a few microns; in any event, a thickness of about 1 micron is sufficient and costs less than do greater thicknesses. It may be possible to grow nitride emitter columns on glass or other substrate materials that cost less than silicon does. What is important in the choice of substrate material is the difference between the substrate and nitride crystalline structures. Inasmuch as the deposition process is nondestructive, an ability to grow emitter columns on a variety of materials would be advantageous in that it would facilitate the integration of field-emitter structures onto previously processed integrated circuits.

Bensaoula, Abdelhak↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

NASA NTRS1982

On implementing self-checking microprocessors

A simple and general model of the interfaces and check circuits used for comparing and detecting faults in a pair of 16-bit processors is described, and problems encountered in the application of TI 9900 processors are discussed. The greatest incompatibility is found to lie between the rollback structures of the CPUs and the interface and check logic (ICL) model. The ICL model generates a reset when an error is detected, and a rollback is expected to occur when it is released. The TI 9900 requires a reset of minimum duration, and after release goes through an initialization cycle, obtains rollback parameters from fixed memory locations, and executes the rollback, consistent with the ICL. The ICL is relatively simple, having a complexity equivalent to fewer than 1000 gates.

Rennels, D. A.↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2011

Binary-Signal Recovery

Binary communication through long cables, opto-isolators, isolating transformers, or repeaters can become distorted in characteristic ways. The usual solution is to slow the communication rate, change to a different method, or improve the communication media. It would help if the characteristic distortions could be accommodated at the receiving end to ease the communication problem. The distortions come from loss of the high-frequency content, which adds slopes to the transitions from ones to zeroes and zeroes to ones. This weakens the definition of the ones and zeroes in the time domain. The other major distortion is the reduction of low frequency, which causes the voltage that defines the ones or zeroes to drift out of recognizable range. This development describes a method for recovering a binary data stream from a signal that has been subjected to a loss of both higher-frequency content and low-frequency content that is essential to define the difference between ones and zeroes. The method makes use of the frequency structure of the waveform created by the data stream, and then enhances the characteristics related to the data to reconstruct the binary switching pattern. A major issue is simplicity. The approach taken here is to take the first derivative of the signal and then feed it to a hysteresis switch. This is equivalent in practice to using a non-resonant band pass filter feeding a Schmitt trigger. Obviously, the derivative signal needs to be offset to halfway between the thresholds of the hysteresis switch, and amplified so that the derivatives reliably exceed the thresholds. A transition from a zero to a one is the most substantial, fastest plus movement of voltage, and therefore will create the largest plus first derivative pulse. Since the quiet state of the derivative is sitting between the hysteresis thresholds, the plus pulse exceeds the plus threshold, switching the hysteresis switch plus, which re-establishes the data zero to one transition, except now at the logic levels of the receiving circuit. Similarly, a transition from a one to a zero will be the most substantial and fastest minus movement of voltage and therefore will create the largest minus first derivative pulse. The minus pulse exceeds the minus threshold, switching the hysteresis switch minus, which re-establishes the data one to zero transition. This innovation has a large increase in tolerance for the degradation of the binary pattern of ones and zeroes, and can reject the introduction of noise in the form of low frequencies that can cause the voltage pattern to drift up or down, and also higher frequencies that are beyond the recognizable content in the binary transitions.

Griebeler, Elmer L.↗

DOE OSTI2020

Strain-engineered high-responsivity MoTe 2 photodetector for silicon photonic integrated circuits

In integrated photonics, specific wavelengths are preferred such as 1550 nm due to low-loss transmission and the availability of optical gain in this spectral region. For chip-based photodetectors, layered two-dimensional (2D) materials bear scientific and technologically relevant properties such as electrostatic tunability and strong light-matter interactions. However, no efficient photodetector in the telecommunication C-band has been realized with 2D transition metal dichalcogenide materials due to their large optical bandgap. Furthermore, we demonstrate a MoTe 2 -based photodetector featuring strong photoresponse (responsivity = 0.5 A/W -1 ) operating at 1550 nm in silicon photonics enabled by strain engineering the 2D material. Non-planarized waveguide structures show a locally-induced bandgap change of 0.2 eV inside MoTe 2 , resulting in large photo-response, in an otherwise photo-inactive medium when unstrained. Unlike Graphene-based photodetectors relying on a gapless band structure, this photodetector shows a ~100X improved dark current, enabling an efficient noise equivalent power of 90 pW/Hz -0.5 . Such strain-engineered integrated photodetector provides new opportunities for integrated optoelectronic systems.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Nonlocal, diamagnetic electromagnetic effects in magnetically insulated transmission lines

We identify the time-dependent physics responsible for the critical reduction of current losses in magnetically insulated transmission lines (MITLs) due to uninsulated space charge-limited currents of electrons emitted by field stress. A drive current of sufficiently short pulse length introduces a strong enough time dependence that steady-state results alone become inadequate for the complete understanding of current losses. The time-dependent physics can be described as a nonlocal, diamagnetic electromagnetic response of space charge limited currents. As the pulse length is increased or equivalently, the MITL length reduced, these time-dependent effects diminish and current losses converge to those predicted by the well-known Child–Langmuir law in the external (vacuum) fields. We present a simple one-dimensional (1D) model that encapsulates the essence of this physics. We find excellent agreement with 2D particle-in-cell simulations for two MITL geometries, Cartesian parallel plate and azimuthally symmetric straight coaxial. Based on the 1D model, we explore various scaling dependencies of MITL losses with relevant parameters, e.g., peak current, pulse length, geometrical dimensions, etc. We propose an improved physics model of magnetic insulation in the form of a Hull curve, which could also help improve predictions of current losses by common circuit element codes, such as BERTHA. Finally, we describe how to calculate the temperature rise due to electron impact within the 1D model.

Computer simulation↗

NASA NTRS1995

Formal development of a clock synchronization circuit

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Miner, Paul S.↗

NASA NTRS1993

Algorithms for high-speed universal noiseless coding

This paper provides the basic algorithmic definitions and performance characterizations for a high-performance adaptive noiseless (lossless) 'coding module' which is currently under separate developments as single-chip microelectronic circuits at two NASA centers. Laboratory tests of one of these implementations recently demonstrated coding rates of up to 900 Mbits/s. Operation of a companion 'decoding module' can operate at up to half the coder's rate. The functionality provided by these modules should be applicable to most of NASA's science data. The hardware modules incorporate a powerful adaptive noiseless coder for 'standard form' data sources (i.e., sources whose symbols can be represented by uncorrelated nonnegative integers where the smaller integers are more likely than the larger ones). Performance close to data entries can be expected over a 'dynamic range' of from 1.5 to 12-15 bits/sample (depending on the implementation). This is accomplished by adaptively choosing the best of many Huffman equivalent codes to use on each block of 1-16 samples. Because of the extreme simplicity of these codes no table lookups are actually required in an implementation, thus leading to the expected very high data rate capabilities already noted.

Rice, Robert F.↗

DOE OSTI2022

Simulating Effective QED on Quantum Computers

In recent years simulations of chemistry and condensed materials has emerged as one of the preeminent applications of quantum computing, offering an exponential speedup for the solution of the electronic structure for certain strongly correlated electronic systems. To date, most treatments have ignored the question of whether relativistic effects, which are described most generally by quantum electrodynamics (QED), can also be simulated on a quantum computer in polynomial time. Here we show that effective QED, which is equivalent to QED to second order in perturbation theory, can be simulated in polynomial time under reasonable assumptions while properly treating all four components of the wavefunction of the fermionic field. In particular, we provide a detailed analysis of such simulations in position and momentum basis using Trotter-Suzuki formulas. We find that the number of T -gates needed to perform such simulations on a 3 D lattice of n s sites scales at worst as O ( n s 3 / ϵ ) 1 + o ( 1 ) in the thermodynamic limit for position basis simulations and O ( n s 4 + 2 / 3 / ϵ ) 1 + o ( 1 ) in momentum basis. We also find that qubitization scales slightly better with a worst case scaling of O ~ ( n s 2 + 2 / 3 / ϵ ) for lattice eQED and complications in the prepare circuit leads to a slightly worse scaling in momentum basis of O ~ ( n s 5 + 2 / 3 / ϵ ) . We further provide concrete gate counts for simulating a relativistic version of the uniform electron gas that show challenging problems can be simulated using fewer than 10 13 non-Clifford operations and also provide a detailed discussion of how to prepare multi-reference configuration interaction states in effective QED which can provide a reasonable initial guess for the ground state. Finally, we estimate the planewave cutoffs needed to accurately simulate heavy elements such as gold.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2020

Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits

Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O (100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm 2 . Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having < 1.0% (equivalent to < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

Alcalde Bessia, Fabricio↗

NASA NTRS2013

New Class of Flow Batteries for Terrestrial and Aerospace Energy Storage Applications

Future sustainable energy generation technologies such as photovoltaic and wind farms require advanced energy storage systems on a massive scale to make the alternate (green) energy options practical. The daunting requirements of such large-scale energy systems such as long operating and cycle life, safety, and low cost are not adequately met by state-of-the-art energy storage technologies such as vanadium flow cells, lead-acid, and zinc-bromine batteries. Much attention is being paid to redox batteries specifically to the vanadium redox battery (VRB) due to their simplicity, low cost, and good life characteristics compared to other related battery technologies. NASA is currently seeking high-specific- energy and long-cycle-life rechargeable batteries in the 10-to-100-kW range to support future human exploration missions, such as planetary habitats, human rovers, etc. The flow batteries described above are excellent candidates for these applications, as well as other applications that propose to use regenerative fuel cells. A new flow cell technology is proposed based on coupling two novel electrodes in the form of solvated electron systems (SES) between an alkali (or alkaline earth) metal and poly aromatic hydrocarbons (PAH), separated by an ionically conducting separator. The cell reaction involves the formation of such SES with a PAH of high voltage in the cathode, while the alkali (or alkaline earth metal) is reduced from such an MPAH complex in the anode half-cell. During recharge, the reactions are reversed in both electrodes. In other words, the alkali (alkaline earth) metal ion simply shuttles from one M-PAH complex (SES) to another, which are separated by a metal-ion conducting solid or polymer electrolyte separator. As an example, the concept was demonstrated with Li-naphthalene//Li DDQ (DDQ is 2,3-Dichloro-5,6-dicyano- 1,4-benzoquinone) separated by lithium super ion conductor, either ceramic or polymer (solid polymer or gel polymer) electrolytes. The reactants are Li-naphthalene dissolved in tetrahydrofuran (THF) with a lithium salt of 1M LiBF4 (lithium tetra fluoroborate) in the anode compartment, and DDQ again dissolved in THF and also containing 1M LiBF4 salt in the cathode half-cell. The solid electrolyte separator used in the first set of experiments is a ceramic solid electrolyte, available from a commercial source. The open circuit voltage of the cells is close to 3.0 V, as expected from the individual half-cell voltages of Li-naphthalene and Li-DDQ. Upon discharge, the cell shows steady discharge voltage of 2.7 V, which confirms that the electrochemical processes do involve lithium ion shuttling from the anodic compartment to the cathode half-cell. The reversibility or rechargeability is demonstrated by charging the partially discharged cells (i.e., with lithium present in the DDQ half). Once again, a steady voltage close to 3.0 V was observed during charge, indicating that the system is quite reversible. In the subsequent concept-demonstration studies, the ceramic electrolyte has been replaced with a gel polymer electrolyte, e.g., PVDF-HFP (poly vinylene difluoride hexafluoropropene) gel, which has several advantages such as high ionic conductivity (almost comparable to liquid electrolyte and about 2 orders of magnitude better than the ceramic equivalent), lower cost, and possibly higher chemical stability at the anode. In addition, it can be bonded to the electrode by thermal fusion to form membrane electrode assemblies (MEAs), as is done in fuel cells.

Bugga, Ratnakumar V.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

This paper describes recent progress at the NASA Glenn Research Center (GRC) in the development and demonstration of an integrated high-propellant throughput small spacecraft electric propulsion (HT-SSEP) system based on a Hall-effect thruster. A center-mounted cathode and an innovative magnetic circuit topology were implemented in the design of the Hall-effect thruster to achieve high-propellant throughput, high performance, and efficient packaging. To minimize technical risk, the HT-SSEP development approach sought to limit design features and materials to those with a clear path-to-flight. A propellant throughput capability of greater than 100 kg at a minimum thruster efficiency of 50% was targeted. The proof-of-concept NASA-H64M laboratory model (LM) thruster was designed, fabricated, and tested at GRC in fiscal year 2018. The thruster development leveraged heritage Hall-effect thruster design and manufacturing processes wherever appropriate. Recent NASA advances in Hall-effect thruster technology were also leveraged. A scalable discharge power supply (DPS) capable of powering the H64M-LM was developed, then demonstrated as part of an integrated system test. The DPS uses commercial off-the-shelf components with spaceflight equivalents. A keeper supply with DC ignitor was breadboarded, then demonstrated with a laboratory cathode. Finally, feed system trade studies were performed to ascertain what feed system architecture might be appropriate for an HT-SSEP system. This paper details the motivations for the project, the development approach, the chosen sub-system architectures, design considerations, and test results.

Benavides, Gabriel F.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

Benavides, Gabriel F.↗