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At least 487 records · Page 27

Shared memory for a fault-tolerant computer

A system is described for sharing a memory in a fault-tolerant computer. The memory is under the direct control and monitoring of error detecting and error diagnostic units in the fault-tolerant computer. This computer verifies that data to and from the memory is legally encoded and verifies that words read from the memory at a desired address are, in fact, actually delivered from that desired address. The means are provided for a second processor, which is independent of the direct control and monitoring of the error checking and diagnostic units of the fault-tolerant computer, and to share the memory of the fault-tolerant computer. Circuitry is included to verify that: (1) the processor has properly accessed a desired memory location in the memory; (2) a data word read-out from the memory is properly coded; and (3) no inactive memory was erroneously outputting data onto the shared memory bus.

Gilley, G. C.↗

Memory page access counts based on page refresh

A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.

97 MATHEMATICS AND COMPUTING↗

Study on advanced information processing system

Issues related to the reliability of a redundant system with large main memory are addressed. In particular, the Fault-Tolerant Processor (FTP) for Advanced Launch System (ALS) is used as a basis for our presentation. When the system is free of latent faults, the probability of system crash due to nearly-coincident channel faults is shown to be insignificant even when the outputs of computing channels are infrequently voted on. In particular, using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs--with a low hardware overhead--can be used to reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, we have developed two schemes, called Scheme 1 and Scheme 2, to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter.

Shin, Kang G.↗

Crystal ball gazing

Over the last seven years, the CPU on my desk has increased speed by two orders of magnitude, from around 1 MIP to more than 100 MIPS; more important is that it is about as fast as any uniprocessor of any type available for any price, for compute bound problems. Memory on the system is also about 100 times as big, while disk is only about 10 times as big. Local network and I/O performance have increased greatly, though not quite at the same rate as processor speed. More important, I will argue, is that the CPU's address space is 64 bits, rather than 32 bits, allowing us to rethink some time honored presumptions. The Internet has gone from a few hundred machines to a million, and now have grown to span the entire globe, and wide area networks have now becoming commercial services. 'PC's' are now real computers, bringing what was top of the line computing capability to the masses only a few years behind the leading edge. So even a year or two from now, we can anticipate commonplace desktop machines running at speeds hundreds of MIPS, with main memories in the hundreds of megabytes to a gigabyte, able to draw millions of vectors/second, and all capable of some reasonable 3D graphics. And only a few years later, this will be the $1500 PC. So the 1990's certainly brings: 64 bit processors becoming standard; BIP/BFLOP class uniprocessors; large scale multiprocessors for special purpose applications; I/O as the most significant computer engineering problem; Hierarchical data servers in everyday use; routine access to archived data around the world; and what else? What do systems such as those we will have this decade imply to those building data analysis systems today? Many of the presumptions of the 1970's and 1980's need to be reexamined in the light of 1990's technology.

Gettys, Jim↗

Exceptional magnetic and magnetoelastic behavior of rare-earth non-centrosymmetric Sm 7 Pd 3

Magnetic compounds possessing an intrinsic combination of near-zero magnetization with high magnetic anisotropy are highly desirable for spinronic applications and memory recording. A comprehensive study of Sm 7 Pd 3 binary compound uncovered a unique combination of strong magnetoelastic behavior, very low net magnetization, and exceptionally high magnetic coercivity. The temperature-dependent X-ray synchrotron powder diffraction study indicates the abrupt changes in the compound's lattice parameters at the magnetic ordering temperature of T C =169 K, although the crystal structure remains non-centrosymmetric hexagonal Th 7 Fe 3 -type down to 6 K. Density functional theory calculations confirm high intrinsic magnetocrystalline anisotropy of Sm 7 Pd 3 , which explains the extremely large coercivity of the polycrystalline sample, up to H cr = 130 kOe at 2 K. In conclusion, this discovery brings to life a novel class of highly anisotropic materials that are distinctly different from known spintronic materials, making them interesting future systems for magnetic memory research.

36 MATERIALS SCIENCE↗

Advanced Engine Cycles Analyzed for Turbofans With Variable-Area Fan Nozzles Actuated by a Shape Memory Alloy

Advanced, large commercial turbofan engines using low-fan-pressure-ratio, very high bypass ratio thermodynamic cycles can offer significant fuel savings over engines currently in operation. Several technological challenges must be addressed, however, before these engines can be designed. To name a few, the high-diameter fans associated with these engines pose a significant packaging and aircraft installation challenge, and a large, heavy gearbox is often necessary to address the differences in ideal operating speeds between the fan and the low-pressure turbine. Also, the large nacelles contribute aerodynamic drag penalties and require long, heavy landing gear when mounted on conventional, low wing aircraft. Nevertheless, the reduced fuel consumption rates of these engines are a compelling economic incentive, and fans designed with low pressure ratios and low tip speeds offer attractive noise-reduction benefits. Another complication associated with low-pressure-ratio fans is their need for variable flow-path geometry. As the design fan pressure ratio is reduced below about 1.4, an operational disparity is set up in the fan between high and low flight speeds. In other words, between takeoff and cruise there is too large a swing in several key fan parameters-- such as speed, flow, and pressure--for a fan to accommodate. One solution to this problem is to make use of a variable-area fan nozzle (VAFN). However, conventional, hydraulically actuated variable nozzles have weight, cost, maintenance, and reliability issues that discourage their use with low-fan-pressure-ratio engine cycles. United Technologies Research, in cooperation with NASA, is developing a revolutionary, lightweight, and reliable shape memory alloy actuator system that can change the on-demand nozzle exit area by up to 20 percent. This "smart material" actuation technology, being studied under NASA's Ultra-Efficient Engine Technology (UEET) Program and Revolutionary Concepts in Aeronautics (RevCon) Program, has the potential to enable the next generation of efficient, quiet, very high bypass ratio turbofans. NASA Glenn Research Center's Propulsion Systems Analysis Office, along with NASA Langley Research Center's Systems Analysis Branch, conducted an independent analytical assessment of this new technology to provide strategic guidance to UEET and RevCon. A 2010-technology-level high-spool engine core was designed for this evaluation. Two families of low-spool components, one with and one without VAFN's, were designed to operate with the core. This "constant core" approach was used to hold most design parameters constant so that any performance differences between the VAFN and fixed nozzle cycles could be attributed to the VAFN technology alone. In this manner, the cycle design regimes that offer a performance payoff when VAFN's are used could be identified. The NASA analytical model of a performance-optimized VAFN turbofan with a fan pressure ratio of 1.28 is shown. Mission analyses of the engines were conducted using the notional, long-haul, advanced commercial twinjet shown. A high wing design was used to accommodate the large high-bypassratio engines. The mission fuel reduction benefit of very high bypass shape-memory-alloy VAFN aircraft was calculated to be 8.3 percent lower than a moderate bypass cycle using a conventional fixed nozzle. Shape-memory-alloy VAFN technology is currently under development in NASA's UEET and RevCon Programs.

Berton, Jeffrey J.↗

Co-design of Advanced Architectures for Graph Analytics using Machine Learning

A graph is an excellent way of representing relationships among entities. We can use graph analytics to synthesize and analyze such relational data, and extract relevant features that are useful for various tasks such as machine learning. Considering the crucial role of graph analytics in various domains, it is important and timely to investigate the right hardware configurations that can achieve optimal performance for graph workloads on future high-performance computing systems. Design space exploration studies facilitate the selection of appropriate configurations (e.g. memory) to achieve a desired system performance. Recently, the approach of accelerating graph analytics using persistent non-volatile memory has gained a lot of attention. Traditional system simulators such as Gem5 and NVMain can be used to explore the design space of these advanced memory architectures for graph workloads. However, these simulators are slow in execution thus limiting the efficiency of design space exploration studies. To overcome this challenge, we proposed a machine learning based approach to co-design advanced memory architectures for graph workloads. We tested our approach with DRAM, non-volatile memory, and hybrid memory (DRAM+NVM) using a breadth first search benchmark algorithm. Our results showed the applicability of the proposed machine learning based approach to the co-design of the advanced memory architectures. In this paper, we provide recommendations on selecting advanced memory architectures to achieve desired performance for graph workloads. We also discuss the performances of different machine learning models that were considered in this study.

Kurte, Kuldeep↗

Tunable Interfacial to Filamentary Resistive Switching Mechanism in Room-Temperature-Grown Amorphous YBa 2 Cu 3 O x with Excess Cu Addition

Resistive switching technologies have the potential not only to create large efficiency gains in computer memory but also to revolutionize emerging fields such as neuromorphic computing. In this paper, we report on novel resistive switching behavior in devices made from room-temperature-grown Cu-rich amorphous YBa 2 Cu 3 O x (YBCO) films, a material otherwise well-known as a high-temperature superconductor. In Nb:STO substrate/amorphous YBCO film (≈200 nm)/metallic Cu (15 nm)/metallic Pt (15 nm) devices, we demonstrate that the resistive switching can be tuned between mechanisms involving extended areas of the YBCO/electrode interface and a single-point filamentary mechanism simply by changing the Cu content of the deposition target and hence in the films. Changing the Cu content can also be used to optimize the properties of the devices further, with devices with an added 15 mol % of Cu in YBCO initially providing an on/off ratio >100, switching endurance potential >6500 cycles, and state retention >2 × 10 4 s, all at low switching fields of 0.3 MV/cm. The amalgam of promising resistive switching properties, fast growth (150 nm/min) at room temperature, and tuneability of the switching mechanism indicates the strong potential of this proof-of-concept amorphous system for future memory applications.

Cu↗

Effect of Gamma Radiation on TaOₓ ECRAM

Electrochemical random access memory (ECRAM) is an emerging three-terminal nonvolatile memory (NVM) with highly controllable channel conductance which is promising for use as an analog memory (or synapse) in analog in-memory computing (IMC) systems. Energy-efficient analog IMC computing is particularly desirable for power-constrained, high-radiation environments such as satellites. However, little is known about the suitability of ECRAM for use in a total ionizing dose (TID) environment. Here, this work investigates the effect of Co-60 gamma radiation on the channel conductance and noise—two properties critical for analog IMC systems—of a TaO x -based ECRAM up to 17.3 Mrad(SiO 2 ) for both low- and high-channel-conductance state devices. A transient increase in conductance is observed in response to radiation which consists of two elements: an immediate increase in conductivity due to photocurrent and a secondary increase in conductivity, which has a slower rise and saturation and can persist for hours after exposure. This secondary, persistent photoconductivity is attributed to charging caused by hole trapping. These transient effects would not likely occur in a space environment due to the low dose rate compared with this experiment. No permanent change is found in the low conductance state (LCS) following exposure and the minor shift in the high conductance change would be less significant than the regular retention decay in this state. A permanent increase in the random telegraph noise is observed, possibly due to increased traps created in the channel. This work demonstrates that TaO x -based ECRAM is suitable for use in spaceborne analog IMC systems that are subject to significant TID.

ECRAM↗

Braiding for the win: Harnessing braiding statistics in topological states to play quantum games

Nonlocal quantum games provide proof of principle that quantum resources can confer an advantage at certain tasks. They also provide a compelling way to explore the computational utility of phases of matter on quantum hardware. In a recent paper [O. Hart et al., Phys. Rev. Lett. 134, 130602 (2025)], we demonstrated that a toric code resource state conferred advantage at a certain nonlocal game, which remained robust to small deformations of the resource state. In this paper we demonstrate that this robust advantage is a generic property of resource states drawn from topological or fracton ordered phases of quantum matter. To this end, we illustrate how several other states from paradigmatic topological and fracton ordered phases can function as resources for suitably defined nonlocal games, notably the three-dimensional toric-code phase, the X-cube fracton phase, and the double-semion phase. The key in every case is to design a nonlocal game that harnesses the characteristic braiding processes of a quantum phase as a source of contextuality. We unify the strategies that take advantage of mutual statistics by relating the operators to be measured to order and disorder parameters of an underlying generalized symmetry-breaking phase transition. Additionally, by connecting the win probability to twist products, we show that success at the game serves as a many-body entanglement witness. Namely, if the players implement a perfect quantum strategy on large length scales, the quantum state they share cannot be connected to a trivial product state via a constant-depth local unitary circuit. Lastly, we massively generalize the family of games that admit perfect strategies when codewords of homological quantum error-correcting codes are used as resources.

Fractons↗

Analysis of Vector Particle-In-Cell (VPIC) memory usage optimizations on cutting-edge computer architectures

Vector Particle-In-Cell (VPIC) is one of the fastest plasma simulation codes in the world, with particle numbers ranging from one trillion on the first petascale system, Roadrunner, to ten trillion particles on the more recent Blue Waters supercomputer. As supercomputers continue to grow rapidly in size, so too does the gap between computing capability and memory capability. Current memory systems limit VPIC simulations greatly as the maximum number of particles that can be simulated directly depends on the available memory. In this study, we present a suite of VPIC memory optimizations (i.e., particle weight, half-precision, and fixed-point optimizations) that enable a significant increase in the number of particles in VPIC simulations. Here, we assess the optimizations’ impact on memory and runtime performance for a suite of cutting-edge computer architectures such has the NVIDIA V100 GPU, the IBM Power9, and the Fujitsu A64FX architectures. Our optimizations enable a 31.25% reduction in memory usage and up to 40% increase in the number of particles. This paper extends our work on developing particle storage format optimizations Tan et al.

97 MATHEMATICS AND COMPUTING↗

Diurnal cycle of precipitation over the tropics and central United States: intercomparison of general circulation models

Diurnal precipitation is a fundamental mode of variability that climate models have difficulty in accurately simulating. Here, in this work, the diurnal cycle of precipitation (DCP) in participating climate models from the Global Energy and Water Exchanges' DCP project is evaluated over the tropics and central United States. Common model biases such as excessive precipitation over the tropics, too frequent light-to-moderate rain, and the failure to capture propagating convection in the central United States still exist. Over the central United States, the issues of too weak rainfall intensity in climate runs is well improved in their hindcast runs with initial conditions from numerical weather prediction analyses. But the improvement is minimal over the central Amazon. Incorporating the role of the large-scale environment in convective triggering processes helps resolve the phase-locking issue in many models where precipitation often incorrectly peaks near noon due to maximum insolation over land. Allowing air parcels to be lifted above the boundary layer improves the simulation of nocturnal precipitation which is often associated with the propagation of mesoscale systems. Including convective memory in cumulus parameterizations acts to suppress light-to-moderate rain and promote intense rainfall; however, it also weakens the diurnal variability. Simply increasing model resolution (with cumulus parameterizations still used) cannot fully resolve the biases of low-resolution climate models in DCP. The hierarchy modeling framework from this study is useful for identifying the missing physics in models and testing new development of model convective processes over different convective regimes.

58 GEOSCIENCES↗

Low-temperature grapho-epitaxial La-substituted BiFeO 3 on metallic perovskite

Bismuth ferrite has garnered considerable attention as a promising candidate for magnetoelectric spin-orbit coupled logic-in-memory. As model systems, epitaxial BiFeO 3 thin films have typically been deposited at relatively high temperatures (650–800 °C), higher than allowed for direct integration with silicon-CMOS platforms. Here, we circumvent this problem by growing lanthanum-substituted BiFeO 3 at 450 °C (which is reasonably compatible with silicon-CMOS integration) on epitaxial BaPb 0.75 Bi 0.25 O 3 electrodes. Notwithstanding the large lattice mismatch between the La-BiFeO 3 , BaPb 0.75 Bi 0.25 O 3 , and SrTiO 3 (001) substrates, all the layers in the heterostructures are well ordered with a [001] texture. Polarization mapping using atomic resolution STEM imaging and vector mapping established the short-range polarization ordering in the low temperature grown La-BiFeO 3 . Current-voltage, pulsed-switching, fatigue, and retention measurements follow the characteristic behavior of high-temperature grown La-BiFeO 3 , where SrRuO 3 typically serves as the metallic electrode. These results provide a possible route for realizing epitaxial multiferroics on complex-oxide buffer layers at low temperatures and opens the door for potential silicon-CMOS integration.

36 MATERIALS SCIENCE↗

Application of mesh refinement to relativistic magnetic reconnection

During relativistic magnetic reconnection, antiparallel magnetic fields undergo a rapid change in topology, releasing a large amount of energy in the form of non-thermal particle acceleration. This work explores the application of mesh refinement to 2D reconnection simulations to efficiently model the inherent disparity in length-scales. We have systematically investigated the effects of mesh refinement and determined necessary modifications to the algorithm required to mitigate non-physical artifacts at the coarse–fine interface. We have used the ultrahigh-order pseudo-spectral analytical time-domain Maxwell solver to analyze how its use can mitigate the numerical dispersion that occurs with the finite-difference time-domain (or “Yee”) method. Absorbing layers are introduced at the coarse–fine interface to eliminate spurious effects that occur with mesh refinement. We also study how damping the electromagnetic fields and current density in the absorbing layer can help prevent the non-physical accumulation of charge and current density at the coarse–fine interface. Using a mesh refinement ratio of 8 for two-dimensional magnetic reconnection simulations, we obtained good agreement with the high-resolution baseline simulation, using only 36% of the macroparticles and 71% of the node-hours needed for the baseline. The methods presented here are especially applicable to 3D systems where higher memory savings are expected than in 2D, enabling comprehensive, computationally efficient 3D reconnection studies in the future.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Differential Power Processing for Ultra-Efficient Data Storage

Here this paper presents the hardware, software, and power codesign of an ultra-efficient data storage server with differential power processing (DPP). DPP can reduce the power conversion stress, improve the efficiency, and enhance the functionality of modular power electronics systems. The power inputs of a large number of hard disk drives (HDDs) were connected in series and supported by a multiport ac-coupled differential power processing (MAC-DPP) converter through a multiwinding transformer. Methods for controlling the multi-input multi-output power flow in the multiwinding transformer while avoiding core saturation were investigated. A ten-port MAC-DPP prototype with 700-W/in 3 power density was built to support a 450-W HDD storage system with ten series-stacked voltage domains. The prototype was tested on a 50-HDD server testbench, and the overall system loss is below 1 W (99.77% system efficiency). The server was able to maintain high-speed reading and writing operation of all 50 HDDs against the worst hot-swapping scenarios. A variety of hardware/software configurations and many cloud storage techniques were tested on the fully functioning server. Experimental results show that the energy efficiency of large-scale information systems (CPU/GPU clusters, memory banks, HDD arrays, etc.) can be greatly improved by software, hardware, and power codesign.

42 ENGINEERING↗

pyDRESCALk

Modern data scientists are tasked to analyze ever-growing data sets with increasingly complex relationships. Tensor decompositions have come to play a central role in identifying underlying latent structures in higher-order data. The problem of fitting tensor models to different distributions is complicated by the combinations of size, dimensionality, and sparsity present in real world data. The situation demands efficient algorithms designed for shared-memory and distributed systems. This work will present new research that tackles these challenges on several different fronts, leveraging optimizations in numerical algorithms and sparse tensor representations in heterogeneous high performance computing environments.

Bhattarai, Manish↗

The Exploitation of Data Reduction for Visualization

The disparity between the computational speed and storage bandwidth, as demonstrated in Figure 1, is a well known problem that grows with each successive generation. The visualization community is principally responding to this issue by using in situ to reduce which data must be written to storage. However, other communities are taking different, possibly complementary approaches. In particular, data compression is a common general approach to reduce storage demands. Data compression technologies are typically not designed with post processing in mind. The principal metrics measured are compression ratio, the improved bandwidth to storage, and the error introduced. It is assumed that data is inflated to its full size before any post processing can happen. Although when talking about bandwidth disparities, HPC’s dirty little secret is that no part of the memory nor interconnect hardware is increasing at the rate of computation. For example, the Summit supercomputer has a peak computation rate almost 10 times its predecessor, Titan, but only about 4 times the memory, less than twice the aggregate memory bandwidth, and almost no improvement in the interconnect bisection bandwidth. Naively inflating data for post processing does not help with limitations in the memory and interconnect systems.

97 MATHEMATICS AND COMPUTING↗