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At least 487 records · Page 27

A genetic algorithms approach for altering the membership functions in fuzzy logic controllers

Through previous work, a fuzzy control system was developed to perform translational and rotational control of a space vehicle. This problem was then re-examined to determine the effectiveness of genetic algorithms on fine tuning the controller. This paper explains the problems associated with the design of this fuzzy controller and offers a technique for tuning fuzzy logic controllers. A fuzzy logic controller is a rule-based system that uses fuzzy linguistic variables to model human rule-of-thumb approaches to control actions within a given system. This 'fuzzy expert system' features rules that direct the decision process and membership functions that convert the linguistic variables into the precise numeric values used for system control. Defining the fuzzy membership functions is the most time consuming aspect of the controller design. One single change in the membership functions could significantly alter the performance of the controller. This membership function definition can be accomplished by using a trial and error technique to alter the membership functions creating a highly tuned controller. This approach can be time consuming and requires a great deal of knowledge from human experts. In order to shorten development time, an iterative procedure for altering the membership functions to create a tuned set that used a minimal amount of fuel for velocity vector approach and station-keep maneuvers was developed. Genetic algorithms, search techniques used for optimization, were utilized to solve this problem.

Shehadeh, Hana↗

Goal-Function Tree Modeling for Systems Engineering and Fault Management

The draft NASA Fault Management (FM) Handbook (2012) states that Fault Management (FM) is a "part of systems engineering", and that it "demands a system-level perspective" (NASAHDBK- 1002, 7). What, exactly, is the relationship between systems engineering and FM? To NASA, systems engineering (SE) is "the art and science of developing an operable system capable of meeting requirements within often opposed constraints" (NASA/SP-2007-6105, 3). Systems engineering starts with the elucidation and development of requirements, which set the goals that the system is to achieve. To achieve these goals, the systems engineer typically defines functions, and the functions in turn are the basis for design trades to determine the best means to perform the functions. System Health Management (SHM), by contrast, defines "the capabilities of a system that preserve the system's ability to function as intended" (Johnson et al., 2011, 3). Fault Management, in turn, is the operational subset of SHM, which detects current or future failures, and takes operational measures to prevent or respond to these failures. Failure, in turn, is the "unacceptable performance of intended function." (Johnson 2011, 605) Thus the relationship of SE to FM is that SE defines the functions and the design to perform those functions to meet system goals and requirements, while FM detects the inability to perform those functions and takes action. SHM and FM are in essence "the dark side" of SE. For every function to be performed (SE), there is the possibility that it is not successfully performed (SHM); FM defines the means to operationally detect and respond to this lack of success. We can also describe this in terms of goals: for every goal to be achieved, there is the possibility that it is not achieved; FM defines the means to operationally detect and respond to this inability to achieve the goal. This brief description of relationships between SE, SHM, and FM provide hints to a modeling approach to provide formal connectivity between the nominal (SE), and off-nominal (SHM and FM) aspects of functions and designs. This paper describes a formal modeling approach to the initial phases of the development process that integrates the nominal and off-nominal perspectives in a model that unites SE goals and functions of with the failure to achieve goals and functions (SHM/FM). This methodology and corresponding model, known as a Goal-Function Tree (GFT), provides a means to represent, decompose, and elaborate system goals and functions in a rigorous manner that connects directly to design through use of state variables that translate natural language requirements and goals into logical-physical state language. The state variable-based approach also provides the means to directly connect FM to the design, by specifying the range in which state variables must be controlled to achieve goals, and conversely, the failures that exist if system behavior go out-of-range. This in turn allows for the systems engineers and SHM/FM engineers to determine which state variables to monitor, and what action(s) to take should the system fail to achieve that goal. In sum, the GFT representation provides a unified approach to early-phase SE and FM development. This representation and methodology has been successfully developed and implemented using Systems Modeling Language (SysML) on the NASA Space Launch System (SLS) Program. It enabled early design trade studies of failure detection coverage to ensure complete detection coverage of all crew-threatening failures. The representation maps directly both to FM algorithm designs, and to failure scenario definitions needed for design analysis and testing. The GFT representation provided the basis for mapping of abort triggers into scenarios, both needed for initial, and successful quantitative analyses of abort effectiveness (detection and response to crew-threatening events).

Patterson, Jonathan D.↗

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗

Management of analytical redundancy in digital flight control systems for aircraft

This paper presents a design method for optimal redundancy management for nonlinear systems with application to highly maneuvering aircraft. The approach taken is based on selecting the failure states to be covered by the system design and constructing a cost function that represents the cost of making an incorrect decision. The decision logic which minimizes the cost requires a bank of extended Kalman filters running in parallel. This produces a severe computational requirement. To reduce this requirement, a suboptimal logic is developed based on using a nonlinear single-stage prediction algorithm in the filters with filter gains and decision logic selected using steady-state results obtained from a linearization of the vehicle and sensor dynamics. The design process is then applied to designing a redundancy management system for the F8-C aircraft. Results indicate that the system is superior in failure detection to a system using the same structure but using a linear single-stage prediction algorithm in the filters.

Montgomery, R. C.↗

Design of a lunar transportation system

The establishment of lunar bases is the next logical step in the exploration of space. Permanent lunar bases will support scientific investigation, the industrialization of space, and the development of self-sufficiency on the Moon. Scientific investigation and research and development would lead to applications utilizing lunar material resources. By utilizing these resources, the industrialization of space can become a reality. The above two factors coupled with the development of key and enabling technologies would lead to achievement of self-sufficiency of the lunar base. Attention was focused on specific design(s) to be pursued during subsequent stages in advanced courses. Some of the objectives in the project included: (1) minimizing the transportation of construction material and fuel from earth, or maximizing the use of the lunar material; (2) use of novel materials and light weight structures; (3) use of new manufacturing methods and technology such as magnetically levitated, or superconducting materials; and (4) innovative concepts of effectively utilizing the exotic lunar conditions, i.e. high thermal gradients, lack of atmosphere, zero wind forces, and lower gravity, etc.

Source record↗

Design issues of a reinforcement-based self-learning fuzzy controller for petrochemical process control

Fuzzy logic controllers have some often-cited advantages over conventional techniques such as PID control, including easier implementation, accommodation to natural language, and the ability to cover a wider range of operating conditions. One major obstacle that hinders the broader application of fuzzy logic controllers is the lack of a systematic way to develop and modify their rules; as a result the creation and modification of fuzzy rules often depends on trial and error or pure experimentation. One of the proposed approaches to address this issue is a self-learning fuzzy logic controller (SFLC) that uses reinforcement learning techniques to learn the desirability of states and to adjust the consequent part of its fuzzy control rules accordingly. Due to the different dynamics of the controlled processes, the performance of a self-learning fuzzy controller is highly contingent on its design. The design issue has not received sufficient attention. The issues related to the design of a SFLC for application to a petrochemical process are discussed, and its performance is compared with that of a PID and a self-tuning fuzzy logic controller.

Yen, John↗

A fuzzy logic intelligent diagnostic system for spacecraft integrated vehicle health management

Due to the complexity of future space missions and the large amount of data involved, greater autonomy in data processing is demanded for mission operations, training, and vehicle health management. In this paper, we develop a fuzzy logic intelligent diagnostic system to perform data reduction, data analysis, and fault diagnosis for spacecraft vehicle health management applications. The diagnostic system contains a data filter and an inference engine. The data filter is designed to intelligently select only the necessary data for analysis, while the inference engine is designed for failure detection, warning, and decision on corrective actions using fuzzy logic synthesis. Due to its adaptive nature and on-line learning ability, the diagnostic system is capable of dealing with environmental noise, uncertainties, conflict information, and sensor faults.

Wu, G. Gordon↗

Redefining Design for Remanufacturing: A Practical Methodology for Prioritizing Remanufacturing Design Rules

Products are often discarded when they fail or no longer meet user needs. These outcomes are frequently shaped by early design decisions. While remanufacturing offers a sustainable alternative by restoring products to like‐new condition, its potential is often limited by designs that do not consider remanufacturing from the outset. This research addresses that challenge by introducing a structured Design for Remanufacturing (DfRem) methodology and a CAD‐integrated tool to support real‐time design decisions. The DfRem framework introduces a new primary design function focused on preserving product functionality across its life cycle. It is supported by a fault tree that identifies failure modes that limit remanufacturing potential and a hierarchy of design principles including Prevent, Minimize, Relocate, Restore, and others. Each principle is linked to actionable design rules that help engineers reduce the need for remanufacturing or improve its efficiency when necessary. To operationalize this framework, we developed CAD plugins for Autodesk Inventor and PTC Creo. These tools use a state machine model to present prioritized design rules based on selected failure modes and user input. By embedding DfRem logic directly into widely used CAD environments, the tool enables engineers to make sustainability‐informed decisions without disrupting existing workflows. Furthermore, this approach highlights the critical role of design in enabling circular and resource‐efficient product development, making remanufacturing a more practical and accessible strategy during the early stages of product design.

CAD↗

Self repair techniques

Computer simulation program for self-repairing system design - reliability improvement as compared to use of redundant logic circuits

SELF-REPAIRING SYSTEM↗

Preliminary design package for Sunspot Domestic Hot Water Heating System

The design review includes a drawing list, auto-control logic, measurement definitions, and other document pertaining to the solar heated prototype hot water systems and two heat exchangers. The hot water systems consist of the following subsystems: collector, storage, control transport, auxiliary energy, and site data acquisition.

Source record↗

A Simplified Shuttle Payload Thermal Analyzer /SSPTA/ program

A simple thermal analysis program for Space Shuttle payloads has been developed to accommodate the user who requires an easily understood but dependable analytical tool. The thermal analysis program includes several thermal subprograms traditionally employed in spacecraft thermal studies, a data management system for data generated by the subprograms, and a master program to coordinate the data files and thermal subprograms. The language and logic used to run the thermal analysis program are designed for the small user. In addition, analytical and storage techniques which conserve computer time and minimize core requirements are incorporated into the program.

Bartoszek, J. T.↗

Investigation of potential of differential absorption Lidar techniques for remote sensing of atmospheric pollutants

The NASA multipurpose differential absorption lidar (DIAL) system uses two high conversion efficiency dye lasers which are optically pumped by two frequency-doubled Nd:YAG lasers mounted rigidly on a supporting structure that also contains the transmitter, receiver, and data system. The DIAL system hardware design and data acquisition system are described. Timing diagrams, logic diagrams, and schematics, and the theory of operation of the control electronics are presented. Success in obtaining remote measurements of ozone profiles with an airborne systems is reported and results are analyzed.

Butler, C. F.↗

Standard Transistor Arrays

Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.

Cox, G. W.↗

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗

Experiment kits for processing biological samples inflight on SLS-2

This paper describes development of an innovative, modular approach to packaging the instruments used to obtain and preserve the inflight rodent tissue and blood samples associated with hematology experiments on the Spacelab Life Sciences-2 (SLS-2) mission. The design approach organized the multitude of instruments into twelve 5- x 6- x l-in. kits which were each used for a particular experiment. Each kit contained the syringes, vials, microscope slides, etc., necessary for processing and storing blood and tissue samples for one rat on a particular day. A total of 1245 components, packaged into 128 kits and stowed in 17 Zero(registered trademark) boxes, were required. Crewmembers found the design easy to use and laid out in a logical, simple configuration which minimized chances for error during the complex procedures in flight. This paper also summarizes inflight performance of the kits on SLS-2.

Savage, P. D.↗

Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.

Fijany, Amir↗

Logic-controlled solid-state switchgear for 270 volt dc.

A feasibility study to design and demonstrate solid-state switchgear composed of circuit breakers and a power transfer switch is described. The switchgear operates on a nominal 270 Vdc circuit and controls power to a load up to 15 A. One circuit breaker may be interconnected to a second to form a power transfer switch. Breaker or switch on-off and transfer functions can be remotely controlled. Automatic overload trip-out is provided through an ultimate current trip and an I squared t trip for transient overcurrents lower than the ultimate current trip level. A number of reclosures with variable time delay between trip-out and reclosure are programmed and controlled by integrated analog and COSMOS logic circuits. A commutation circuit that creates minimal transient disturbances to either source or load was developed to interrupt current flow through the main SCR switching element.-

Waddington, D.↗