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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 487 records · Page 27
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

A Real-Time Optical Ground Receiver for Photon Starved Environments

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) has developed a photon-counting optical ground receiver for pulse-position modulated signals. The real-time receiver system includes a fiber interconnect, superconducting nanowire single-photon detectors (SNSPDs), and a real-time field programmable gate array (FPGA) based receiver. The fiber interconnect and SNSPDs are implemented with two different configurations. In the first, a 7-channel few-mode fiber photonic lantern couples the light from the telescope to 7 single-pixel few-mode fiber coupled SNSPDs. In the second configuration, a few-mode fiber couples light to a 16-pixel monolithic SNSPD array. The real-time FPGA-based receiver performs combining of up to 16 SNSPD channels, symbol timing recovery, demodulation, and decoding. The system is scalable with data rates ranging from 20 Mbps to 267 Mbps. It is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Standard. This standard will be used in NASA deep space and other low photon flux missions, such as in the Orion Artemis-2 Optical Communications System (O2O) demonstration, planned for the first crewed flight of Orion. This paper describes the scalable real-time optical receiver system and presents characterization test results.

optical communications↗
NASA NTRSDate not supplied

A Real-Time Optical Ground Receiver for Photon Starved Environments

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) has developed a photon-counting optical ground receiver for pulse-position modulated signals. The real-time receiver system includes a fiber interconnect, superconducting nanowire single-photon detectors (SNSPDs), and a real-time field programmable gate array (FPGA) based receiver. The fiber interconnect and SNSPDs are implemented with two different configurations. In the first, a 7-channel few-mode fiber photonic lantern couples the light from the telescope to 7 single-pixel few-mode fiber coupled SNSPDs. In the second configuration, a few-mode fiber couples light to a 16-pixel monolithic SNSPD array. The real-time FPGA-based receiver performs combining of up to 16 SNSPD channels, symbol timing recovery, demodulation, and decoding. The system is scalable with data rates ranging from 20 Mbps to 267 Mbps. It is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Standard. This standard will be used in NASA deep space and other low photon flux missions, such as in the Orion Artemis-2 Optical Communications System (O2O) demonstration, planned for the first crewed flight of Orion. This paper describes the scalable real-time optical receiver system and presents characterization test results.

optical communications↗
NASA NTRSDate not supplied

Laser Communications Relay Demonstration Optimetrics Experiment

Within this paper, we report on an Optimetrics experiment conducted on the National Aeronautics and Space Administration (NASA) Laser Communication Relay Demonstration (LCRD). The high precision two-way ranging is conducted on the optical communications link between the LCRD space terminal in a geosynchronous orbit and the Optical Ground Station 1 (OGS1) at Table Mountain, California, and is referred to as optimetrics ranging. The receiver to transmitter clock loopback is implemented in the LCRD space modem. A digital dual mixer time difference phase meter (DDMTD) is implemented in the OGS1 ground modem. The round-trip time is measured with the DDMTD by counting the frame and data clock ticks between transmitter and receiver frame synchronization markers for coarse range, and the relative phase of the transmit and receive clock for high precision range. This approach provides coverage for all potential ranges with no ranging ambiguity. The flight modem FPGA code was modified for frame and data clock loopback and the OGS1 FPGA code was modified for the DDMTD phase meter implementation. The experiment team conducted a 36-hour continuous ranging measurement. Preliminary two-way optimetrics ranging data show a noise floor of 3cm (rms). Based on our theoretical noise analysis and ground tests with spare flight modems, we expected one order of magnitude improvement on ranging precision. We are conducting detailed post data processing to identify the differences to further reduce the noise level and formulating an improved implementation approach for future missions. For reference and comparison, traditional Radio Frequency (RF) ranging between LCRD and OGS1 was conducted at the same time and indicates a ranging noise floor of 30cm(rms). Other telemetry and relevant environmental parameters such as weather and atmosphere temperature were also collected for offline data processing. The high precision ranging and range rate measurements from the laser communications data link clock and clock phase are performed simultaneously with continuous optical communication. No extra hardware added to existing system. This high precision optimetrics measurement implementation provides alternative ranging and range rate measurements for orbit determination (OD) and flight dynamics calculations with higher precision. We see significant improvement on OD for navigation upon implementation in future optical communication systems.

Rafael Garcia↗
NASA NTRSDate not supplied

A Photon Counting Ground Receiver for Free-Space Optical Communications

The National Aeronautics and Space Administration is developing a photon counting ground receiver for free-space optical communications. The receiver consists of a fiber interconnect, superconducting nanowire single photon counting detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. This receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency standard, which is used in the low photon flux communications regime, including on the upcoming Optical Artemis-2 Orion communications demonstration. The receiver architecture is modular, can be scaled for data rate, and is designed with primarily commercial-off-the-shelf technology. Two fiber interconnect and detector architectures are being prototyped. The first uses a few-mode-fiber coupled to a 16-channel SNSPD array and the second architecture uses a photonic lantern coupled to 7 single-pixel SNSPDs. Photon counting, symbol timing recovery, demodulation and decoding is done using several FPGA cards. This presentation describes the unique features of the ground receiver, performance test results, and challenges with using commercial SNSPDs in free-space optical communications.

Jennifer N Downey↗
NASA NTRS2024

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗
DOE OSTI2021

Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning

Although Transformer-based language representations achieve state-of-the-art accuracy on various natural language processing (NLP) tasks, the large model size has been challenging the resource constrained computing platforms. Weight pruning, as a popular and effective technique in reducing the number of weight parameters and accelerating the Transformer, has been investigated on GPUs. However, the Transformer acceleration using weight pruning on field-programmable gate array (FPGAs) remains unexplored. This paper investigates the column balanced block-wise pruning on Transformer and designs an FPGA acceleration engine to customize the balanced blockwise matrix multiplication. We implement the Transformer model with proper hardware scheduling, and the experiments show that the Transformer inference on FPGA achieves 10.35 ms latency with the batch size of 32, which is 10.96 × speed up comparing to CPU platform and 2.08 × speed up comparing to GPU platform.

Peng, Hongwu↗
DOE OSTI2021

hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices

Accessible machine learning algorithms, software, and diagnostic tools for energy-efficient devices and systems are extremely valuable across a broad range of application domains. In scientific domains, real-time near-sensor processing can drastically improve experimental design and accelerate scientific discoveries. To support domain scientists, we have developed hls4ml, an open-source software-hardware codesign workflow to interpret and translate machine learning algorithms for implementation with both FPGA and ASIC technologies. We expand on previous hls4ml work by extending capabilities and techniques towards low-power implementations and increased usability: new Python APIs, quantization-aware pruning, end-to-end FPGA workflows, long pipeline kernels for low power, and new device backends include an ASIC workflow. Taken together, these and continued efforts in hls4ml will arm a new generation of domain scientists with accessible, efficient, and powerful tools for machine-learning-accelerated discovery.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Digital Q-Meter for continuous-wave NMR

A method to perform continuous-wave NMR measurements of nuclear magnetization at high magnetic fields, above 2.5 T, without analog down-mixing is described. An FPGA controls a digital clock pulse which is used to stimulate a resonant circuit and provide a reference signal. An algorithm determines the real portion of a resonant circuit signal near the Larmor frequency of the species of interest using only two measurements of the waveform per cycle. The FPGA automatically alters a variable capacitance to tune the resonant circuit to the Larmor frequency.

Maxwell, James↗
DOE OSTI2024

A Graph Neural Network Surrogate Model for hls4ml

Recent advancements in use of machine learning (ML) techniques on field-programmable gate arrays (FPGAs) have allowed for the implementation of embedded neural networks with extremely low latency. This is invaluable for particle detectors at the Large Hadron Collider, where latency and used area are strictly bounded. The hls4ml framework is a procedure that converts trained ML model software to a synthesis result to can be used on an FPGA. However, running the pipeline is a time-consuming procedure, and there is a strong risk of failure. In particular, it may not be possible to successfully convert a model into a synthesis result, or the resource consumption of the model may exceed the resources of the target FPGA. To aid with this development, we introduce wa-hls4ml, a surrogate model using a graph neural network to emulate the structure of the source models. The goal is to estimate the chance of success and resource consumption of a given model when passed through the hls4ml pipeline, without needing to run the pipeline.

Plotnikov, Dennis↗
DOE OSTI2025

Development of BPM electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗
DOE OSTI2025

Obsidian

Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.

Moore, Victoria [Lawrence Berkeley National Labora↗
DOE OSTI2025

Sub-microsecond Transformers for Jet Tagging on FPGAs

We present the first sub-microsecond transformer implementation on an FPGA achieving competitive performance for state-of-the-art high-energy physics benchmarks. Transformers have shown exceptional performance on multiple tasks in modern machine learning applications, including jet tagging at the CERN Large Hadron Collider (LHC). However, their computational complexity prohibits use in real-time applications, such as the hardware trigger system of the collider experiments up until now. In this work, we demonstrate the first application of transformers for jet tagging on FPGAs, achieving $\mathcal{O}(100)$ nanosecond latency with superior performance compared to alternative baseline models. We leverage high-granularity quantization and distributed arithmetic optimization to fit the entire transformer model on a single FPGA, achieving the required throughput and latency. Furthermore, we add multi-head attention and linear attention support to hls4ml, making our work accessible to the broader fast machine learning community. This work advances the next-generation trigger systems for the High Luminosity LHC, enabling the use of transformers for real-time applications in high-energy physics and beyond.

Laatu, Lauri [Imperial Coll., London]↗
DOE OSTI2026

Exploration of Real Time Inference for MI-RR Deblending on GPU/TPU Systems

The Fermilab Main Injector (MI) and Recycler Ring (RR) share a common beam loss monitor (BLM) system, making loss events difficult to attribute to their source machine when beam is present in both simultaneously. The Real-time Edge AI for Distributed Systems (READS) project addresses this by deblending BLM readings in real time using machine learning (ML). The current FPGA based implementation meets the sub-3 ms latency requirement but carries a resource intensive hls4ml development cycle, motivating exploration of GPU based deployment. This paper characterizes inference latency on an NVIDIA Jetson Orin Nano and introduces a packet organization scheme for assembling synchronized event frames from seven distributed BLM DAQ streams. Using a Python based DAQ simulation with injected timing jitter in place of unavailable live beam data, the pipeline achieved an average end to end latency of 0.456 ms (σ = 0.122 ms) across 167,000 test frames, comfortably meeting the timing constraint. Early outliers were attributed to TensorRT warm-up rather than steady state limitations, suggesting GPU based inference is a viable alternative to the existing FPGA implementation.

Yu, Kellen [Fermilab; Cornell U.]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2026

CAPTAN+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗
DOE OSTI2023

Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml

Abstract Recurrent neural networks have been shown to be effective architectures for many tasks in high energy physics, and thus have been widely adopted. Their use in low-latency environments has, however, been limited as a result of the difficulties of implementing recurrent architectures on field-programmable gate arrays (FPGAs). In this paper we present an implementation of two types of recurrent neural network layers—long short-term memory and gated recurrent unit—within the hls4ml framework. We demonstrate that our implementation is capable of producing effective designs for both small and large models, and can be customized to meet specific design requirements for inference latencies and FPGA resources. We show the performance and synthesized designs for multiple neural networks, many of which are trained specifically for jet identification tasks at the CERN Large Hadron Collider.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Neural architecture codesign for fast physics applications

We develop a pipeline to streamline neural architecture codesign for physics applications to reduce the need for ML expertise when designing models for novel tasks. Our method employs neural architecture search and network compression in a two-stage approach to discover hardware efficient models. This approach consists of a global search stage that explores a wide range of architectures while considering hardware constraints, followed by a local search stage that fine-tunes and compresses the most promising candidates. We exceed performance on various tasks and show further speedup through model compression techniques such as quantization-aware-training and neural network pruning. We synthesize the optimal models to high level synthesis code for FPGA deployment with the hls4ml library. Additionally, our hierarchical search space provides greater flexibility in optimization, which can easily extend to other tasks and domains. We demonstrate this with two case studies: Bragg peak finding in materials science and jet classification in high energy physics, achieving models with improved accuracy, smaller latencies, or reduced resource utilization relative to the baseline models.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗