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CMOS decoder is assembled from standard 4-line to 16-line decoder/demultiplexer IC's. Matrix may also be used to generate 256 latched-on or latched-off logic signals instead of 512 discrete unlatched signals. By using conventional CMOS IC's, circuit consumes only about 30 milliwatts.
Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.
A 12 bit successive approximation analog to digital converter that offers moderately high speed precision data conversion at a reasonable level of cost and complexity is studied. The ADCH10HT extends this capability over a temperature range of -55 to +200 C. No missing-code performance is maintained over the entire temperature range. The converter is completely self-contained with internal clock and +10 volt reference. The CMOS devices offer low power dissipation, so that the internal temperature of the hybrid circuit does not rise as much from self heating. In CMOS circuits, pn junction leakage currents are returned to the supplies so that the logic keeps working at temperatures up to 250 C.
An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 x 10 to the 5th rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.
An account is given of a Get-Away-Special experiment flown on Space Shuttles 7 and 8 investigating the effect of the space environment on Shumann emulsions. Shumann emulsions, having low gelatin content and no protective gelatin overcoating, are useful detectors of ultraviolet radiation shorter than 2200 angstroms but are extremely sensitive to environmental conditions and handling. The instrument required no interface with the Shuttle. It was turned on by an aneroid switch at an altitude of 50,000 feet. After that, its operation was controlled completely by a CMOS digital controller. Each hour, two temperatures and one voltage were read and stored in a CMOS programmable read only memory. At intervals, valves were opened and closed to expose SO 652 film strips of three sensitivities to the cargo bay environment for various time periods. The design and operation of the instrument package is described.
The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.
A summary of single event upset data for 42 device types (including RAMs, 4-bit slices, microprocessors, 4-bit counters, and flip-flops) studied at 11 different accelerator tests (performed chiefly with the Berkeley 88-inch cyclotron and the Cal Tech Van de Graaff) is presented. All bipolar and NMOS RAMs were found to be SEU sensitive, some with very low LET thresholds. Some CMOS or CMOS/SOS RAMs were hard; and the CMOS microprocessors were hard, but the bipolar and NMOS microprocessors were soft. Several devices were found to exhibit a cross section that depends strongly on LET, even when the LET is well above the LET threshold. A ranking of hardness is presented for the logic devices tested.
Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips.
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
A major problem in the qualification of integrated circuit cells and in the development of adequate tests for the circuits is to lack of information on the nature and density of fault models. Some of this information is being obtained from the test structures. In particular, the Pinhole Array Capacitor is providing values for the resistance of gate oxide shorts, and the Addressable Inverter Matrix is providing values for parameter distributions such as noise margins. Another CMOS fault mode, that of the open-gated transistor, is examined and the state of the transistors assessed. Preliminary results are described for a number of open-gated structures such as transistors, inverters, and NAND gates. Resistor faults are applied to various CMOS gates and the time responses are noted. The critical value for the resistive short to upset the gate response was determined.
An electronic timer has been developed for sounding rocket use. The timer uses CMOS technology for low power consumption and has a battery back-up to keep the timing circuit active in case of a dropout on the payload power bus. Time-event decoding is done by programming EPROM's which enable a +28 volt dc sourcing output. There are 32 discrete outputs which can provide +28 volt dc into a minimum load impedance of 150 ohms. Inputs are designed to operate on standard CMOS voltage levels, but they can withstand +28 volts dc without damage. The timer can be started by either 'G' or lift-off switch closure or umbilical release at lift-off.
A photometer capable of automatically measuring ozone concentration data to very high resolution during scientific research flights in the Earth's atmosphere was developed at NASA Ames Research Center. This instrument was recently deployed to study the ozone hole over Antarctica. Ozone is detected by absorbing 253.7-nm radiation from an ultraviolet lamp which shines through the sample of air and impinges on a vacuum phototube. A lower output from the phototube indicates more ozone present in the air sample. The photometer employs a CMOS Z80 microprocessor with an STD bus system for experiment control, data collection, and storage. Data are collected and stored in nonvolatile memory for experiments lasting up to 8 hr. Data are downloaded to a portable ground-support computer and processed after the aircraft lands. An independent single-board computer in the STD bus also calculates ozone concentration in real time with less resolution than the CMOS Z80 system, and sends this value to a cockpit meter to aid the pilot in navigation.
Theoretical study takes new look at current-vs.-voltage behavior of silicon controlled rectifiers (SCR's), four-layer complementary metal oxide/semiconductor (CMOS) devices, and similar devices susceptible to latchup. For purposes of analysis, "latchup" denotes transition of such device from lower-current-conducting steady state to distinct higher-current-conducting steady state. Focuses upon conventional two-couple-transistor model of one-dimensional SCR. Although model gives oversimplified view of latchup in CMOS circuits, useful for qualitative predictions of electrical characteristics.
A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.
A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.
A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.
The development of two 256 by 256 hybrid HgCdTe focal plane array (FPA) families is described, and their performance is discussed. The hybrid FPAs employ a PV HgCdTe detector array and custom Si CMOS readouts. The PACE-1 process was used to fabricate the detectors, whereby the liquid phase epitaxial growth of HgCdTe occurs on sapphire substrates buffered by a layer of CdTe. The performance characteristics of the detector arrays are given. A tactical 256 by 256 CMOS readout is tested, in which a high functional yield was achieved. Updated test results are given for a 256 by 256 readout circuit developed for use in an orbital replacement instrument for the Hubble Space Telescope. The characterizations of several MWIR and SWIR FPAs were thorough and shown to be reliable. The pixel yield, maximum FPA responsivity nonuniformity, and SWIR FPA read noise for the tests are given. The high contrast and insignificant fixed pattern noise of the imagery from the MWIR 256 by 256 FPA are emphasized. These qualities were obtained when the device was operating at 80 k and utilizing f/2 optics with an 8-in. focal length and a 4.4 micron high pass filter.
This paper reports a single 8.2mm by 8.4mm, 200,000 transistor CMOS chip implementation of the Reed Solomon code required by the Space Telescope. The chip features a 10 MHz sustained byte rate independent of error pattern. The 1.6 micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with programmable corrections of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors.