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At least 487 records · Page 27

Initial application of CAP-TSD to wing flutter

The initial application of the CAP-TSD computer program for wing flutter analysis is presented. Computational Aeroelasticity Program - Transonic Small Disturbance (CAP-TSD) is based on an approximate factorization (AF) algorithm that is stable and efficient on supercomputers with vector arithmetic. CAP-TSD was used to calculate steady and unsteady pressures on wings and configurations at subsonic, transonic, and supersonic Mach numbers. However, the CAP-TSD code has been developed primarily for aeroelastic analysis. The initial efforts for validation of the aeroelastic analysis capability is presented. The initial applications include two series of symmetric, planar wing planforms. Well defined modal properties are available for these wings. In addition, transonic flutter boundaries are available for evaluation of the transonic capabilities of CAP-TSD.

Cunningham, Herbert J.↗

Transformation based endorsement systems

Evidential reasoning techniques classically represent support for a hypothesis by a numeric value or an evidential interval. The combination of support is performed by an arithmetic rule which often requires restrictions to be placed on the set of possibilities. These assumptions usually require the hypotheses to be exhausitive and mutually exclusive. Endorsement based classification systems represent support for the alternatives symbolically rather than numerically. A framework for constructing endorsement systems is presented in which transformations are defined to generate and update the knowledge base. The interaction of the knowledge base and transformations produces a non-monotonic reasoning system. Two endorsement based reasoning systems are presented to demonstrate the flexibility of the transformational approach for reasoning with ambiguous and inconsistent information.

Sudkamp, Thomas↗

Limitations on K-T mass extinction theories based upon the vertebrate record

Theories of extinction are only as good as the patterns of extinction that they purport to explain. Often such patterns are ignored. For the terminal Cretaceous events, different groups of organisms in different environments show different patterns of extinction that to date cannot be explained by a single causal mechanism. Several patterns of extinction (and/or preservational bias) can be observed for the various groups of vertebrates from the uppermost Cretaceous Hell Creek Formation and lower Paleocene Tullock Formation in eastern Montana. The taxonomic level at which the percentage of survivals (or extinctions) is calculated will have an effect upon the perception of faunal turnover. In addition to the better known mammals and better publicized dinosaurs, there are almost 60 additional species of reptiles, birds, amphibians, and fish in the HELL Creek Formation. Simple arithmetic suggests only 33 percent survival of these vertebrates from the Hell Creek Fm. into the Tullock Fm. A more critical examination of the data shows that almost all Hell Creek species not found in the Tullock are represented in one of the following categories; extremely rare forms, elasmobranch fish that underwent rapid speciation taxa that although not known or rare in the Tullock, are found elsewhere. Each of the categories is largely the result of the following biases: taphonomy, ecological differences, taxonomic artifact paleogeography. The two most important factors appear to be the possible taphonomic biases and the taxonomic artifacts. The extinction patterns among the vertebrates do not appear to be attributable to any single cause, catastrophic or otherwise.

Archibald, J. David↗

Alaska SAR Facility (ASF5) SAR Communications (SARCOM) Data Compression System

The real-time operational requirements for SARCOM translation into a high speed image data handler and processor to achieve the desired compression ratios and the selection of a suitable image data compression technique with as low as possible fidelity (information) losses and which can be implemented in an algorithm placing a relatively low arithmetic load on the system are described.

Mango, Stephen A.↗

The Fault Tree Compiler (FTC): Program and mathematics

The Fault Tree Compiler Program is a new reliability tool used to predict the top-event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, AND m OF n gates. The high-level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precisely (within the limits of double precision floating point arithmetic) within a user specified number of digits accuracy. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Equipment Corporation (DEC) VAX computer with the VMS operation system.

Butler, Ricky W.↗

Benchmarking and performance analysis of the CM-2

A suite of benchmarking routines testing communication, basic arithmetic operations, and selected kernel algorithms written in LISP and PARIS was developed for the CM-2. Experiment runs are automated via a software framework that sequences individual tests, allowing for unattended overnight operation. Multiple measurements are made and treated statistically to generate well-characterized results from the noisy values given by cm:time. The results obtained provide a comparison with similar, but less extensive, testing done on a CM-1. Tests were chosen to aid the algorithmist in constructing fast, efficient, and correct code on the CM-2, as well as gain insight into what performance criteria are needed when evaluating parallel processing machines.

Myers, David W.↗

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Mcmillan, Gary B.↗

Exact computation of the unwrapped phase of a finite-length time series

McGowan and Kuc (1982) showed that a direct relationship between a time series and its unwrapped phase exists. They proposed an algorithm for computing the unwrapped phase by counting the number of sign changes in a Sturm sequence generated from the real and imaginary parts of the discrete Fourier transform. Their algorithm is limited to relatively short sequences by numerical accuracy. An extension of their algorithm is proposed which, by using all-integer arithmetic, permits exact computation of the number of multiples of pi required to determine the unwrapped phase for rational-valued time sequences of arbitrary length. Since the computation is exact, the extended numerical algorithm should be of interest when accurate phase unwrapping is required.

Long, David G.↗

BLITZEN - A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗

Optical systems for digit-serial computation

High-accuracy optical systems for implementing digit-serial computations are discussed which incorporate parallelism and carry-free addition to achieve high processing speed. Employing on-line arithmetic, parallel calculations can be performed by the concurrent execution of operations. The algorithms are shown to be problem invariant and step invariant. Architectures using optical bistable devices and optical interconnects are discussed which can implement digit-serial addition, subtraction, multiplication, and division algorithms via the present approach.

Perlee, Caroline J.↗

Simplified Correlator For Ranging Codes

Improved correlating subsystem of pseudorandom-code ranging system made possible by advent of fast, custom-made, very-large-scale integrated circuits. Performs far fewer arithmetical operations, contains much less specialized analog and digital circuitry, and used with large number of different codes.

Tausworthe, R. C.↗

Managing Information On Costs

Cost Management Model, CMM, software tool for planning, tracking, and reporting costs and information related to costs. Capable of estimating costs, comparing estimated to actual costs, performing "what-if" analyses on estimates of costs, and providing mechanism to maintain data on costs in format oriented to management. Number of supportive cost methods built in: escalation rates, production-learning curves, activity/event schedules, unit production schedules, set of spread distributions, tables of rates and factors defined by user, and full arithmetic capability. Import/export capability possible with 20/20 Spreadsheet available on Data General equipment. Program requires AOS/VS operating system available on Data General MV series computers. Written mainly in FORTRAN 77 but uses SGU (Screen Generation Utility).

Taulbee, Zoe A.↗

Modeling and control system design and analysis tools for flexible structures

Described here are Boeing software tools used for the development of control laws of flexible structures. The Boeing Company has developed a software tool called Modern Control Software Package (MPAC). MPAC provides the environment necessary for linear model development, analysis, and controller design for large models of flexible structures. There are two features of MPAC which are particularly appropriate for use with large models: (1) numerical accuracy and (2) label-driven nature. With the first feature MPAC uses double precision arithmetic for all numerical operations and relies on EISPAC and LINPACK for the numerical foundation. With the second feature, all MPAC model inputs, outputs, and states are referenced by user-defined labels. This feature allows model modification while maintaining the same state, input, and output names. In addition, there is no need for the user to keep track of a model variable's matrix row and colunm locations. There is a wide range of model manipulation, analysis, and design features within the numerically robust and flexible environment provided by MPAC. Models can be built or modified using either state space or transfer function representations. Existing models can be combined via parallel, series, and feedback connections; and loops of a closed-loop model may be broken for analysis.

Anissipour, Amir A.↗

Optimal q-Markov COVER for finite precision implementation

The existing q-Markov COVER realization theory does not take into account the problems of arithmetic errors due to both the quantization of states and coefficients of the reduced order model. All q-Markov COVERs allow some freedom in the choice of parameters. Here, researchers exploit this freedom in the existing theory to optimize the models with respect to these finite wordlength effects.

Williamson, Darrell↗

BLITZEN: A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗

Efficient algorithms for dilated mappings of binary trees

The problem is addressed to find a 1-1 mapping of the vertices of a binary tree onto those of a target binary tree such that the son of a node on the first binary tree is mapped onto a descendent of the image of that node in the second binary tree. There are two natural measures of the cost of this mapping, namely the dilation cost, i.e., the maximum distance in the target binary tree between the images of vertices that are adjacent in the original tree. The other measure, expansion cost, is defined as the number of extra nodes/edges to be added to the target binary tree in order to ensure a 1-1 mapping. An efficient algorithm to find a mapping of one binary tree onto another is described. It is shown that it is possible to minimize one cost of mapping at the expense of the other. This problem arises when designing pipelined arithmetic logic units (ALU) for special purpose computers. The pipeline is composed of ALU chips connected in the form of a binary tree. The operands to the pipeline can be supplied to the leaf nodes of the binary tree which then process and pass the results up to their parents. The final result is available at the root. As each new application may require a distinct nesting of operations, it is useful to be able to find a good mapping of a new binary tree over existing ALU tree. Another problem arises if every distinct required binary tree is known beforehand. Here it is useful to hardwire the pipeline in the form of a minimal supertree that contains all required binary trees.

Iqbal, M. Ashraf↗

Transient fault behavior in a microprocessor: A case study

An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made.

Duba, Patrick↗

A nearly-linear computational-cost scheme for the forward dynamics of an N-body pendulum

The dynamic equations of motion of an n-body pendulum with spherical joints are derived to be a mixed system of differential and algebraic equations (DAE's). The DAE's are kept in implicit form to save arithmetic and preserve the sparsity of the system and are solved by the robust implicit integration method. At each solution point, the predicted solution is corrected to its exact solution within given tolerance using Newton's iterative method. For each iteration, a linear system of the form J delta X = E has to be solved. The computational cost for solving this linear system directly by LU factorization is O(n exp 3), and it can be reduced significantly by exploring the structure of J. It is shown that by recognizing the recursive patterns and exploiting the sparsity of the system the multiplicative and additive computational costs for solving J delta X = E are O(n) and O(n exp 2), respectively. The formulation and solution method for an n-body pendulum is presented. The computational cost is shown to be nearly linearly proportional to the number of bodies.

Chou, Jack C. K.↗