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At least 469 records · Page 26
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Micromachined silicon cantilever beam accelerometer incorporating an integrated optical waveguide

A micromachined cantilever beam accelerometer is described in which beam deflection is determined optically. A diving board structure is anisotropically etched into a silicon wafer. This diving board structure is patterned from the wafer backside so as to leave a small gap between the tip of the diving board and the opposite fixed edge on the front side of the wafer. In order to sense a realistic range of accelerations, a foot mass incorporated onto the end of the beam is found to provide design flexibility. A silicon nitride optical waveguide is then deposited by low pressure chemical vapor deposition (LPCVD) onto the sample. Beam deflection is measured by the decrease of light coupled across the gap between the waveguide sections. In order to investigate sensor response and simulate deflection of the beam, we utilized a separate beam and waveguide section which could be displaced from one another in a precisely controlled manner. Measurements were performed on samples with gaps of 4.0, 6.0, and 8.0 micron and the variation of the fraction of light coupled across the gap as a function of displacement and gap spacing was found to agree with overlap integral calculations.

Burcham, Kevin E.↗
NASA NTRS1995

The growth of cubic silicon carbide on a compliant substrate

Research has shown that silicon carbide grown on silicon and 6H silicon carbide has problems associated with these substrates. This is because silicon and silicon carbide has a 20% lattice mismatch and cubic silicon carbide has not been successfully achieved on 6H silicon carbide. We are investigating the growth of silicon carbide on a compliant substrate in order to grow defect free silicon carbide. This compliant substrate consists of silicon/silicon dioxide with 1200 A of single crystal silicon on the top layer. We are using this compliant substrate because there is a possibility that the silicon dioxide layer and the carbonized layer will allow the silicon lattice to shrink or expand to match the lattice of the silicon carbide. This would improve the electrical properties of the film for the use of device fabrication. When trying to grow silicon carbide, we observed amorphous film. To investigate, we examined the process step by step using RHEED. RHEED data showed that each step was amorphous. We found that just by heating the substrate in the presence of hydrogen it changed the crystal structure. When heated to 1000 C for 2 minutes, RHEED showed that there was an amorphous layer on the surface. We also heated the substrate to 900 C for 2 minutes and RHEED data showed that there was a deterioration of the single crystalline structure. We assumed that the presence of oxygen was coming from the sides of the silicon dioxide layer. Therefore, we evaporated 2500 A of silicon to all four edges of the wafer to try to enclose the oxygen. When heating the evaporated wafer to 900 C the RHEED data showed single crystalline structure however at 1000 C the RHEED data showed deterioration of the single crystalline structure. We conclude that the substrate itself is temperature dependent and that the oxygen was coming from the sides of the silicon dioxide layer. We propose to evaporate more silicon on the edges of the wafer to eliminate the escape of oxygen. this will allow us to grow single crystal cubic silicon carbide.

Mitchell, Sharanda↗
NASA NTRS1995

Diffusion lengths in irradiated N/P InP-on-Si solar cells

Indium phosphide (InP) solar cells are being made on silicon (Si) wafers (InP/Si) to take advantage of both the radiation-hardness properties of the InP solar cell and the light weight and low cost of Si wafers compared to InP or germanium (Ge) wafers. The InP/Si cell application is for long duration and/or high radiation orbit space missions. InP/Si cells have higher absolute efficiency after a high radiation dose than gallium arsenide (GaAs) or silicon (Si) solar cells. In this work, base electron diffusion lengths in the N/P cell are extracted from measured AM0 short-circuit photocurrent at various irradiation levels out to an equivalent 1 MeV fluence of 1017 1 MeV electrons/sq cm for a 1 sq cm 12% BOL InP/Si cell. These values are then checked for consistency by comparing measured Voc data with a theoretical Voc model that includes a dark current term that depends on the extracted diffusion lengths.

Wojtczuk, Steven↗
NASA NTRS1997

A Feasibility Study to Control Airfoil Shape Using THUNDER

The objective of this study was to assess the capabilities of a new out-of-plane displacement piezoelectric actuator called thin-layer composite-unimorph ferroelectric driver and sensor (THUNDER) to alter the upper surface geometry of a subscale airfoil to enhance performance under aerodynamic loading. Sixty test conditions, consisting of combinations of five angles of attack, four dc applied voltages, and three tunnel velocities, were studied in a tabletop wind tunnel. Results indicated that larger magnitudes of applied voltage produced larger wafer displacements. Wind-off displacements were also consistently larger than wind-on. Higher velocities produced larger displacements than lower velocities because of increased upper surface suction. Increased suction also resulted in larger displacements at higher angles of attack. Creep and hysteresis of the wafer, which were identified at each test condition, contributed to larger negative displacements for all negative applied voltages and larger positive displacements for the smaller positive applied voltage (+102 V). An elastic membrane used to hold the wafer to the upper surface hindered displacements at the larger positive applied voltage (+170 V). Both creep and hysteresis appeared bounded based on the analysis of several displacement cycles. These results show that THUNDER can be used to alter the camber of a small airfoil under aerodynamic loads.

Pinkerton, Jennifer L.↗
NASA NTRS1998

Design, Operation, and Modeling of a Vertical APCVD Reactor for Silicon Carbide Film Growth

An atmospheric pressure chemical vapor deposition (APCVD) reactor utilizing a unique vertical geometry which enables 3C-SiC films to be grown on two, 4-inch diameter Si wafers has been constructed. Contrary to expectations, 3C-SiC films grown in this reactor are thickest at the downstream end of the substrates. To better understand the reason for the thickness distribution on the wafers, an axisymmetric finite-element model of the gas flow in the reactor was constructed. The model uses the ANSYS53 Flowtran package and includes compressible and temperature-dependent fluid properties in laminar or turbulent flow. It does not include reaction chemistry or unsteady flow. The ANSYS53 results predict that the cool, inlet fluid falls through the inlet pipe and the warm, diffuser region like a jet. This jet impinges on top of the susceptor and gets diverted to the reactor side walls, where it flows to the bottom of the reactor, turns, and slowly rises along the face of the susceptor. This may explain why the SiC films are thickest at the downstream side of the wafers, as gas containing fresh reactants first passes over this region. Modeling results are presented for both one atmosphere and one half atmosphere reactor pressure.

DeAnna, Russell G.↗
NASA NTRS2001

Etching in Chlorine Discharges Using an Integrated Feature Evolution-Plasma Model

Etching of semiconductor materials is reliant on plasma properties. Quantities such as ion and neutral fluxes, both in magnitude and in direction, are often determined by reactor geometry (height, radius, position of the coils, etc.) In order to obtain accurate etching profiles, one must also model the plasma as a whole to obtain local fluxes and distributions. We have developed a set of three models that simulates C12 plasmas for etching of silicon, ion and neutral trajectories in the plasma, and feature profile evolution. We have found that the location of the peak in the ion densities in the reactor plays a major role in determining etching uniformity across the wafer. For a stove top coil inductively coupled plasma (ICP), the ion density is peaked at the top of the reactor. This leads to nearly uniform neutral and ion fluxes across the wafer. A side coil configuration causes the ion density to peak near the sidewalls. Ion fluxes are thus greater toward the wall's and decrease toward the center. In addition, the ions bombard the wafer at a slight angle. This angle is sufficient to cause slanted profiles, which is highly undesirable.

Hwang, Helen H.↗
NASA NTRS2002

A Statistical Analysis of Laser Ablated Ba(Sub 0.50)Sr(Sub 0.50)TiO(Sub 3)/LaAlO(Sub 3) Films for Microwave Applications

The NASA Glenn Research Center is constructing a 616 element scanning phased array antenna using thin film Ba(sub x)Sr(sub 1-x)TiO(sub 3) based phase shifters. A critical milestone is the production of 616 identical phase shifters at 19 GHz with [asymptotically equal to]4 dB insertion loss and at least 337.5 deg phase shift with 3 percent bandwidth. It is well known that there is a direct relationship between dielectric tuning and loss due to the Kramers-Kronig relationship and that film crystallinity and strain, affected by the substrate template, play an important role. Ba(sub 0.50)Sr(sub 0.50)TiO (sub 3) films, nominally 400 nm thick, were deposited on 48 0.25 mm thick, 5 cm diameter LaAlO(sub 3) wafers. Although previous results suggested that Mn-doped films on MgO were intrinsically superior in terms of phase shift per unit loss, for this application phase shift per unit length was more important. The composition was selected as a compromise between tuning and loss for room temperature operation (e.g. crystallinity progressively degrades for Ba concentrations in excess of 30 percent). As a prelude to fabricating the array, it was necessary to process, screen, and inventory a large number of samples. Variable angle ellipsometry was used to characterize refractive index and film thickness across each wafer. Microstructural properties of the thin films were characterized using high resolution X-ray diffractometry. Finally, prototype phase shifters and resonators were patterned on each wafer and RE probed to measure tuning as a function of dc bias voltage as well as peak (0 field) permittivity and unloaded Q. The relationship among film quality and uniformity and performance is analyzed. This work presents the first statistically relevant study of film quality and microwave performance and represents a milestone towards commercialization of thin ferroelectric films for microwave applications.

Ferroelectric thin films↗
NASA NTRS2004

High Temperature Propulsion System Structural Seals for Future Space Launch Vehicles

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA s Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two types of seal preloading devices were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. 1000 cycles) of scrubbing at 1600 F against an Inconel 625 rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were up to 32 times lower than those recorded for the best braided rope seal flow blockers. Canted coil springs and silicon nitride compression springs showed promise conceptually as potential seal preloading devices to help maintain seal resiliency. A finite element model of the canted coil spring revealed that it should be possible to produce a spring out of high temperature materials for applications at 2000+ F.

Dunlap, Patrick H., Jr.↗
NASA NTRS2003

High Temperature Propulsion System Structural Seals for Future Space Launch Vehicles

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA's Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two types of seal preloading devices were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. (1000 cycles) of scrubbing at room temperature against an Inconel 625 rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were much lower than those recorded for the best braided rope seal flow blockers. Canted coil springs and silicon nitride compression springs showed promise conceptually as potential seal preloading devices to help maintain seal resiliency. A finite element model of the canted coil spring revealed that it should be possible to produce a spring out of high temperature materials for applications at 2000+ F.

Dunlap, Patrick H., Jr.↗
NASA NTRS2004

Further Investigations of Hypersonic Engine Seals

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA's Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. (50.8 m) of scrubbing at 2000 F against a silicon carbide rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were up to 32 times lower than those recorded for the best braided rope seal flow blockers. Silicon nitride compression springs showed promise conceptually as potential seal preload devices to help maintain seal resiliency.

Dunlap, Patrick H., Jr.↗
NASA NTRS1996

Silicon Carbide High-Temperature Power Rectifiers Fabricated and Characterized

The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.

Source record↗
NASA NTRS2004

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Speer, Kevin M.↗
NASA NTRS2004

Web Growth Used to Confine Screw Dislocations to Predetermined Lateral Positions in 4H-SiC Epilayers

Silicon-carbide- (SiC-) based power devices could enable substantial aerospace electronics benefits over today's silicon-based electronics. However, present-day SiC wafers contain electrically harmful dislocations (including micropipes) that are unpredictably distributed in high densities across all commercial 4H- and 6H-SiC wafers. The NASA Glenn Research Center recently demonstrated a crystal growth process that moves SiC wafer dislocations to predetermined lateral positions in epitaxial layers so that they can be reproducibly avoided during subsequent SiC electronic device fabrication. The process starts by reactive ion etching mesa patterns with enclosed trench regions into commercial on-axis (0001) 4H- or 6H-SiC substrates. An example of a pregrowth mesa geometry with six enclosed triangular-shaped trench regions is shown. After the etch mask is stripped, homoepitaxial growth is carried out in pure stepflow conditions that enable thin cantilevers to grow laterally from the tops of mesas whose pregrowth top surfaces are not threaded by substrate screw dislocations. The image in the bottom figure shows the postgrowth structure that forms after the lateral cantilevers expand to coalesce and completely roof over each of the six triangular trench regions. Atomic force microscope (AFM) measurements of the roof revealed that three elementary screw dislocation growth spirals, each shown in the AFM insets of the bottom image on the previous page, formed in the film roof at three respective points of cantilever film coalescence. The image above shows the structure following an etch in molten potassium hydroxide (KOH) that produced surface etch pits at the dislocation defects. The larger KOH etch pits--S1, S2, and S3--shown in this image correspond to screw dislocations relocated to the final points of cantilever coalescence. The smaller KOH etch pits are consistent with epilayer threading edge dislocations from the pregrowth substrate mesa (P1, P3, and P4) and a final cantilever coalescence point (P2). No defects (i.e., no etch pits) are observed in other cantilevered portions of the film surface. On the basis of the principle of dislocation Burgers vector conservation, we hypothesize that all vertically propagating substrate dislocations in an enclosed trench region become combined into a single dislocation in the webbed film roof at the point of final roof coalescence. The point of final roof coalescence, and therefore the lateral location of a webbed roof dislocation, can be designed into the pregrowth mesa pattern. Screw dislocations with predetermined lateral positions can then be used to provide the new growth steps necessary for growing a 4H/6H-SiC epilayer with a lower dislocation density than the substrate. Devices fabricated on top of such films can be positioned to avoid the preplaced dislocations.

Powell, J. Anthony↗
NASA NTRS2005

Beyond G-band : a 235 GHz InP MMIC amplifier

We present results on an InP monolithic millimeter- wave integrated circuit (MMIC) amplifier having 10-dB gain at 235 GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technology's (NGST) 0.07- m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325 GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for -parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230 GHz.

high electron mobility transistors (HEMTs)↗
NASA NTRS2007

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Allen, Christine↗
NASA NTRS2002

Microgyroscope with integrated vibratory element

A microgyroscope having a suspended vertical post uses the Coriolis force to detect the rotation rate. The microgyroscope consists of a single vertical post which is the rotation rate sensing element. The vertical post is formed from the same silicon wafers as the rest of the microgyroscope. A first portion of the vertical post and the clover-leaf structure are made from a first silicon wafer. A second portion of the vertical post and the baseplate are made from a second silicon wafer. The two portions are then bonded together to from the clover-leaf gyroscope with an integrated post structure.

Tang, Tony K.↗
NASA NTRS2005

Method of producing an integral resonator sensor and case

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Shcheglov, Kirill V.↗
NASA NTRS1987

Method of fabricating a PbS-PbSe IR detector array

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Barrett, John R.↗