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At least 469 records · Page 26

All sources NASA NTRS DOE OSTI

NASA NTRS2010

Localized Triple Modular Redundancy vs. Distributed Triple Modular Redundancy on a ProASIC3E Reprogrammable FPGA

Field programmable gate arrays (FPGA) are used in every space application. Currently, most space flight applications use radiation hardened (RH) FPGAs, which are very expensive. There is a desire to use cheaper, commercial off the shelf reprogrammable FPGAs, which are more susceptible to radiation effects known as single-event effects (SEE). The RH parts have SEE and total ionizing dose (TID) hardened elements pre-integrated into the part. This means that the designer does not need to implement any hardening techniques while configuring the device. The COTS parts on the other hand must be mitigated by design in order to insure any form of mitigation. The design techniques this project examines concern the use of localized triple modular redundancy (LTMR) and distributed triple modular redundancy (DTMR). LTMR triples every flip flop in the device architecture while DTMR triples everything except for the global routes (clocks, resets, and enables). The testing was performed on a ProASIC3E FPGA at the Texas A&M cyclotron facility. Two design architectures were used: shift registers and counters, both with LTMR and DTMR mitigation techniques. The test results prove that DTMR is more effective at reducing SEE than LTMR. We also determined that there was not a significant difference between the use of shift registers and counters for test purposes. More testing is required to obtain additional linear energy transfer values for each architecture and mitigation technique in order to determine the most cost-effective method of SEE mitigation.

McGuffey, Alex↗

NASA NTRS1977

An active thermal compensator for closed-cycle helium refrigerators

A technique was developed for reducing the amplitude of the temperature oscillation in He closed-cyle refrigerators. The device uses a semiconductor diode as a heating element to actively supply a small oscillating input of heat at a point between the laser and the cold-tip to cancel the heat oscillations due to the refrigerator. It was found that the heater diode could drive the temperature of the heat sink more effectively, i.e., with lower current and therefore less heat, if the heat sink was insulated slightly from the rest of the mount. A sine-wave generator was used to drive the programmable supply which provided the offset current to the heater diode. By matching the frequency and phase of the oscillator to that of the refrigerator cycle, and by adjusting the amplitude of the oscillator signal, the temperature fluctuations at the laser could be minimized. Residual fluctuations were about 0.003K peak-to-peak, at an operating temperature of 9.5K.

Jennings, D. E.↗

NASA NTRS2002

EZStream: Distributing Live ISS Experiment Telemetry via Internet

This paper will present the high-level architecture and components of the current version of EZStream as well as the product direction & enhancements to be incorporated through a Phase II grant. Security will be addressed such as data encryption and user login. Remote user devices will be discussed including web browsers on PC's and displays on PDA's and smart cell phones. The interaction between EZStream and TReK will be covered as well as the eventuality of EZStream to receive and parse binary data streams directly. This makes EZStream beneficial to both the International Partners and non-NASA applications. The options of developing client-side display web pages will be addressed and the development of new tools to allow creation of display web pages by non-programmers.

Myers, Gerry↗

DOE OSTI2024

Energy efficient photonic memory based on electrically programmable embedded III-V/Si memristors: switches and filters

Abstract Over the past few years, extensive work on optical neural networks has been investigated in hopes of achieving orders of magnitude improvement in energy efficiency and compute density via all-optical matrix-vector multiplication. However, these solutions are limited by a lack of high-speed power power-efficient phase tuners, on-chip non-volatile memory, and a proper material platform that can heterogeneously integrate all the necessary components needed onto a single chip. We address these issues by demonstrating embedded multi-layer HfO 2 /Al 2 O 3 memristors with III-V/Si photonics which facilitate non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers, and (de-)interleaver filters. The Mach-Zehnder optical memristor exhibits non-volatile optical phase shifts > π with ~33 dB signal extinction while consuming 0 electrical power consumption. We demonstrate 6 non-volatile states each capable of 4 Gbps modulation. (De-) interleaver filters were demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and beyond. We demonstrate non-volatile III-V/Si optical memristors with large electric-field driven phase shifts and reconfigurable filters with true 0 static power consumption. As a result, co-integrated photonic memristors offer a pathway for in-memory optical computing and large-scale non-volatile photonic circuits.

Cheung, Stanley (ORCID:0000000248860013)↗

DOE OSTI2023

Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials

The Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic devices that are based on resistive-switching materials, such as memristors and electrochemical RAM. Equally important, Abisko uses a deep codesign approach to pursue this goal by engaging experts from across the entire range of disciplines: materials, devices and circuits, architectures and integration, software, and algorithms. Here, the key objectives of our Abisko project are threefold. First, we are designing an energy-optimized high-performance neuromorphic accelerator based on SNNs. This architecture is being designed as a chiplet that can be deployed in contemporary computer architectures and we are investigating novel neuromorphic materials to improve its design. Second, we are concurrently developing a productive software stack for the neuromorphic accelerator that will also be portable to other architectures, such as field-programmable gate arrays and GPUs. Third, we are creating a new deep codesign methodology and framework for developing clear interfaces, requirements, and metrics between each level of abstraction to enable the system design to be explored and implemented interchangeably with execution, measurement, a model, or simulation. As a motivating application for this codesign effort, we target the use of SNNs for an analog event detector for a high-energy physics sensor.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1995

Development of 3-Phase CCD Timing Generator

Charge-Coupled Devices (CCDs) are used in a wide range of commercial, scientific, and defense applications. They are primarily utilized for imaging and spectroscopic functions. Compact, cost-effective technology to miniaturize the auxiliary electronics required to operate the CCD is highly desirable. Because of the importance of reducing size and weight in defense and space applications, emphasis must be placed on the reduction in size. The purpose of this project is to minimize the CCD timing generator electronics for 3-phase CCDs by replacing conventional ICs with a single programmable IC. This timing generator will give the user the ability to vary the number of horizontal and vertical pixels and to choose between integration and readout modes. This, in turn, will reduce the size and weight of CCD focal plane assemblies as a whole.

Bennett, Kory L.↗

NASA NTRS2009

Electrically Variable or Programmable Nonvolatile Capacitors

Electrically variable or programmable capacitors based on the unique properties of thin perovskite films are undergoing development. These capacitors show promise of overcoming two important deficiencies of prior electrically programmable capacitors: Unlike in the case of varactors, it is not necessary to supply power continuously to make these capacitors retain their capacitance values. Hence, these capacitors may prove useful as components of nonvolatile analog and digital electronic memories. Unlike in the case of ferroelectric capacitors, it is possible to measure the capacitance values of these capacitors without changing the values. In other words, whereas readout of ferroelectric capacitors is destructive, readout of these capacitors can be nondestructive. A capacitor of this type is a simple two terminal device. It includes a thin film of a suitable perovskite as the dielectric layer, sandwiched between two metal or metal oxide electrodes (for example, see Figure 1). The utility of this device as a variable capacitor is based on a phenomenon, known as electrical-pulse-induced capacitance (EPIC), that is observed in thin perovskite films and especially in those thin perovskite films that exhibit the colossal magnetoresistive (CMR) effect. In EPIC, the application of one or more electrical pulses that exceed a threshold magnitude (typically somewhat less than 1 V) gives rise to a nonvolatile change in capacitance. The change in capacitance depends on the magnitude duration, polarity, and number of pulses. It is not necessary to apply a magnetic field or to cool the device below (or heat it above) room temperature to obtain EPIC. Examples of suitable CMR perovskites include Pr(1-x)Ca(x)MnO3, La(1-x)S-r(x)MnO3,and Nb(1-x)Ca(x)MnO3. Figure 2 is a block diagram showing an EPIC capacitor connected to a circuit that can vary the capacitance, measure the capacitance, and/or measure the resistance of the capacitor.

Shangqing, Liu↗

NASA NTRS2011

Monitoring Digital Closed-Loop Feedback Systems

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

Katz, Richard↗

NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗

DOE OSTI2020

Quantitative and Predictive Genetic Parts for Plant Synthetic Biology

Plant synthetic biology aims to harness the natural abilities of plants and to turn them to new purposes. A primary goal of plant synthetic biology is to produce predictable and programmable genetic circuits from simple regulatory elements and well-characterized genetic components. The number of available DNA parts for plants is increasing, and the methods for rapid quantitative characterization are being developed, but the field of plant synthetic biology is still in its early stages. We here describe methods used to describe the quantitative properties of genetic components needed for plant synthetic biology. Once the quantitative properties and transfer function of a variety of genetic parts are known, computers can select the optimal components to assemble into functional devices, such as toggle switches and positive feedback circuits. However, while the variety of circuits and traits that can be put into plants are limitless, doing synthetic biology in plants poses unique challenges. Plants are composed of differentiated cells and tissues, each representing potentially unique regulatory or developmental contexts to introduced synthetic genetic circuits. Further, plants have evolved to be highly sensitive to environmental influences, such as light or temperature, any of which can affect the quantitative function of individual parts or whole circuits. Measuring the function of plant components within the context of a plant cell and, ideally, in a living plant, will be essential to using these components in gene circuits with predictable function. Mathematical modeling will be needed to account for the variety of contexts a genetic part will experience in different plant tissues or environments. With such understanding in hand, it may be possible to redesign plant traits to serve human and environmental needs.

59 BASIC BIOLOGICAL SCIENCES↗

NASA NTRS1985

Design of high-voltage, high-power, solid state remote power controllers for aerospace applications

Two general types of remote power controllers (RPC's), which combine the functions of a circuit breaker and a switch, were developed for use in dc aerospace systems. Power-switching devices used in the designs are the gate-turnoff thyristor (GTO) and MOSFET. The RPC's can switch dc voltages to 1200 V and currents to 1000 A. Seven different units were constructed and subjected to laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times which limit surge currents and voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout proportional to I sq T and microsecond tripout for large overloads.

Sturman, J. C.↗

DOE OSTI2022

CyOTE ASSET OWNER ENGAGEMENT – SIDE CHANNEL POWER ANALYSIS PROTOTYPE

The U.S. Department of Energy’s (DOE) Office of Cybersecurity, Energy Security, and Emergency Response (CESER), through the Cybersecurity for the Operational Technology Environment (CyOTE) Program, worked with energy sector asset owners and operators (AOOs), partners, and Idaho National Laboratory (INL) to develop capabilities for AOOs to independently identify adversarial tactics, techniques, and procedures (TTPs) within their operational technology (OT) environments. The CyOTE methodology seeks to identify adversarial techniques within an AOO OT environment that could result in physical disruptions to energy flow or damage to equipment. CyOTE provides a general roadmap for AOOs, starting from a triggering event, or the point in time and space they perceive an anomalous event or condition meriting investigation, and culminating when the AOO has sufficient confidence to make a business risk decision on the appropriate resolution. This paper outlines the results of one such engagement with the New York Power Authority (NYPA), where the CyOTE program partnered with an AOO to develop a design specification for a power side channel detector to identify anomalous changes to device load. It describes the goal of developing this capability, the development process, the challenges the technical teams faced and the future steps an AOO will need to take to install and use this detector in its OT environment.

99 GENERAL AND MISCELLANEOUS↗

NASA NTRS1992

Electronic Still Camera

A handheld, programmable, digital camera is disclosed that supports a variety of sensors and has program control over the system components to provide versatility. The camera uses a high performance design which produces near film quality images from an electronic system. The optical system of the camera incorporates a conventional camera body that was slightly modified, thus permitting the use of conventional camera accessories, such as telephoto lenses, wide-angle lenses, auto-focusing circuitry, auto-exposure circuitry, flash units, and the like. An image sensor, such as a charge coupled device ('CCD') collects the photons that pass through the camera aperture when the shutter is opened, and produces an analog electrical signal indicative of the image. The analog image signal is read out of the CCD and is processed by preamplifier circuitry, a correlated double sampler, and a sample and hold circuit before it is converted to a digital signal. The analog-to-digital converter has an accuracy of eight bits to insure accuracy during the conversion. Two types of data ports are included for two different data transfer needs. One data port comprises a general purpose industrial standard port and the other a high speed/high performance application specific port. The system uses removable hard disks as its permanent storage media. The hard disk receives the digital image signal from the memory buffer and correlates the image signal with other sensed parameters, such as longitudinal or other information. When the storage capacity of the hard disk has been filled, the disk can be replaced with a new disk.

Holland, S. Douglas↗

NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗

DOE OSTI2024

Construction of Reconfigurable and Polymorphic DNA Origami Assemblies with Coiled‐Coil Patches and Patterns

Abstract DNA origami nanodevices achieve programmable structure and tunable mechanical and dynamic properties by leveraging the sequence‐specific interactions of nucleic acids. Previous advances have also established DNA origami as a useful building block to make well‐defined micron‐scale structures through hierarchical self‐assembly, but these efforts have largely leveraged the structural features of DNA origami. The tunable dynamic and mechanical properties also provide an opportunity to make assemblies with adaptive structures and properties. Here the integration of DNA origami hinge nanodevices and coiled‐coil peptides are reported into hybrid reconfigurable assemblies. With the same dynamic device and peptide interaction, it is made multiple higher‐order assemblies (i.e., polymorphic assembly) by organizing clusters of peptides into patches or arranging single peptides into patterns on the surfaces of DNA origami to control the relative orientation of devices. The coiled‐coil interactions are used to construct circular and linear assemblies whose structure and mechanical properties can be modulated with DNA‐based reconfiguration. Reconfiguration of linear assemblies leads to micron scale motions and ≈2.5‐10‐fold increase in bending stiffness. The results provide a foundation for stimulus‐responsive hybrid assemblies that can adapt their structure and properties in response to nucleic acid, peptide, protein, or other triggers.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2021

Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs

Offloading computation from a CPU to a hardware accelerator is becoming a more common solution for improving performance because traditional gains enabled by Moore’s law and Dennard scaling have slowed. GPUs are often used as hardware accelerators, but field-programmable gate arrays (FPGAs) are gaining traction. FPGAs are beneficial because they allow hardware specific to a particular application to be created. However, they are notoriously difficult to program. To this end, two of the main FPGA manufacturers, Intel and Xilinx, have created tools and frameworks that enable the use of higher level languages to design FPGA hardware. Although Xilinx kernels can be designed by using C/C++, both Intel and Xilinx support the use of OpenCL C to architect FPGA hardware. However, not much is known about the portability and performance between these two device families other than the fact that it is theoretically possible to synthesize a kernel meant for Intel to Xilinx and vice versa.In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We use OpenCL C implementations of a subset of the Rodinia benchmarking suite that were designed for an Intel FPGA and make the necessary modifications to create synthesizable OpenCL C kernels for a Xilinx FPGA. We find that the difficulty of porting certain kernel optimizations varies, depending on the construct. Once the minimum amount of modifications is made to create synthesizable hardware for the Xilinx platform, more nontrivial work is needed to improve performance. However, we find that constructs that are known to be performant for an FPGA should improve performance regardless of the platform; the difficulty comes in deciding how to invoke certain kernel optimizations while also abiding by the constraints enforced by a given platform’s hardware compiler.

Cabrera, Anthony↗

NASA NTRS1999

Advanced Design and Implementation of a Control Architecture for Long Range Autonomous Planetary Rovers

An advanced design and implementation of a Control Architecture for Long Range Autonomous Planetary Rovers is presented using a hierarchical top-down task decomposition, and the common structure of each design is presented based on feedback control theory. Graphical programming is presented as a common intuitive language for the design when a large design team is composed of managers, architecture designers, engineers, programmers, and maintenance personnel. The whole design of the control architecture consists in the classic control concepts of cyclic data processing and event-driven reaction to achieve all the reasoning and behaviors needed. For this purpose, a commercial graphical tool is presented that includes the mentioned control capabilities. Messages queues are used for inter-communication among control functions, allowing Artificial Intelligence (AI) reasoning techniques based on queue manipulation. Experimental results show a highly autonomous control system running in real time on top the JPL micro-rover Rocky 7 controlling simultaneously several robotic devices. This paper validates the sinergy between Artificial Intelligence and classic control concepts in having in advanced Control Architecture for Long Range Autonomous Planetary Rovers.

Martin-Alvarez, A.↗

NASA NTRS2003

ASRC Aerospace Corporation Selects Dynamically Reconfigurable Anadigm(Registered Trademark) FPAA For Advanced Data Acquisition System

Anadigm(registered trademark) today announced that ASRC Aerospace Corporation has designed Anadigm's dynamically reconfigurable Field Programmable Analog Array (FPAA) technology into an advanced data acquisition system developed under contract for NASA. ASRC Aerospace designed in the Anadigm(registered trademark) FPAA to provide complex analog signal conditioning in its intelligent, self-calibrating, and self-healing advanced data acquisition system (ADAS). The ADAS has potential applications in industrial, manufacturing, and aerospace markets. This system offers highly reliable operation while reducing the need for user interaction. Anadigm(registered trademark)'s dynamically reconfigurable FPAAs can be reconfigured in-system by the designer or on the fly by a microprocessor. A single device can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. In the case of the ASRC advanced data acquisition system, the FPAA helps ensure that the system will continue to operating at 100% functionality despite changes in the environment, component degradation, and/or component failures.

Mata, Carlos T.↗