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At least 469 records · Page 26

All sources NASA NTRS DOE OSTI

NASA NTRS2003

Integrated Electrode Arrays for Neuro-Prosthetic Implants

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Brandon, Erik↗

NASA NTRS1986

Predicting the Cosmic-Ray Environment Near Earth

Package of computer programs developed to predict cosmic-ray environment for spacecraft in orbit near Earth. Single cosmic-ray particle deposits enough electrical charge on sensitive area of individual circuit to change bit state. Single-event upsets may not cause permanent damage but upset functioning devices. Used to predict upset rate for space mission. Also calculates time-average cosmic-ray environment for multiple circular orbits, fragments of trajectories, and isolated points. Package written in HPL for interactive execution and implemented on HP 9825B desktop computer.

Edmonds, L.↗

NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗

NASA NTRS1998

Analysis of a Memory Device Failure

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Nicolas, David P.↗

DOE OSTI2021

A Double-side Cooled SiC MOSFET Power Module with Sintered-silver Interposers: I. Design, Simulation, Fabrication, and Performance Characterization

Planar, double-side cooled power modules are emerging in electric-drive inverters because of their low profile, better heat extraction, and lower package parasitic inductances. However, there is still concern about their reliability due to the rigid interconnection between the device chips and two substrates of the power module. In this paper, a porous interposer made of low-temperature sintered silver is introduced to reduce the thermo-mechanical stresses in the module. A double-side cooled half-bridge module consisting of two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using the sintered-Ag instead of solid copper interposers, our simulation results showed that at a total power loss of 200 W, the thermo-mechanical stress at the most vulnerable interfaces (interposer-attach layer) was reduced by 42 % and in the SiC MOSFET by 50 % with a trade-off of only 3.6 % increase in junction temperature. The sintered-Ag interposers were readily fabricated into desired dimensions without post-machining and did not require any surface finishing for die-bonding and substrate interconnection by silver sintering. Here, the porous interposers were also deformable under a low force or pressure, which helped to accommodate chip thickness and/or substrate-to-substrate gap variations in the planar module structure, thus simplifying module fabrication. Experimental results on the electrical performance of the fabricated SiC modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.

42 ENGINEERING↗

DOE OSTI2024

300_underground robot (final research report)

Recent advancements in mobile robotics have displayed impressive capabilities in traversing and accessing areas that are inaccessible to humans either due to the characteristics of the environment or potential hazards. Furthermore, these advancements within the field of mobile robotics, more specifically uncrewed ground vehicles (UGVs), give the ability to potentially survey, observe, and map these inaccessible areas for humans. However, one of the most challenging areas to implement this technology is underground environments. The main challenge with implementing this technology in underground environments is the dependence on either GPS or RF communication for UGVs to navigate properly. Therefore, in order to properly demonstrate the mapping capabilities of the UGV this challenge must be resolved. The overall goal of this study is to demonstrate the mapping capabilities of a UGV while addressing this challenge and documenting the implementation and testing phase of the robot. The proposed solution to this challenge is to implement a SLAM algorithm onto the main computational device of the UGV utilizing the Robot Operating System (ROS). The algorithm is the open-source software package Slam Toolbox developed by Steve Macenski. Furthermore, the sllidar_ros2 package from Slamtec will be used to gather the lidar data from an A3M1 2D lidar. A separate program will be created to gather odometry information for our UGV robot. All of these software packages will run together in a Docker environment. Through working on this project I have developed a better understanding of the world of robotics/autonomous systems, especially with applications such as navigation and mapping. Furthermore, through this project, I have been given exposure to how research is conducted within a DOE lab setting. As robotics/autonomous systems become more advanced it's important to pursue more avenues of research such as this project as it will ensure the development of our capabilities.

42 ENGINEERING↗

NASA NTRS1972

Miniature biotelemeter gives multichannel wideband biomedical data

A miniature biotelemeter was developed for sensing and transmitting multiple channels of biomedical data over a radio link. The design of this miniature, 10-channel, wideband (5 kHz/channel), pulse amplitude modulation/ frequency modulation biotelemeter takes advantage of modern device technology (e.g., integrated circuit operational amplifiers, complementary symmetry/metal oxide semiconductor logic, and solid state switches) and hybrid packaging techniques. The telemeter is being used to monitor 10 channels of neuron firings from specific regions of the brain in rats implanted with chronic electrodes. Design, fabrication, and testing of an engineering model biotelemeter are described.

Carraway, J. B.↗

NASA NTRS2000

Evaluation of Thermo-Mechanical Stability of COTS Dual-Axis MEMS Accelerometers for Space Applications

Microelectromechanical systems in MEMS is one of the fastest growing technologies in microelectronics, and is of great interest for military and aerospace applications. Accelerometers are the earliest and most developed representatives of MEMS. First demonstrated in 1979, micromachined accelerometers were used in automobile industry for air bag crash- sensing applications since 1990. In 1999, N4EMS accelerometers were used in NASA-JPL Mars Microprobe. The most developed accelerometers for airbag crash- sensing are rated for a full range of +/- 50 G. The range of sensitivity for accelerometers required for military or aerospace applications is much larger, varying from 20,000 G (to measure acceleration during gun and ballistic munition launches), and to 10(exp -6) G, when used as guidance sensors (to measure attitude and position of a spacecraft). The presence of moving parts on the surface of chip is specific to MEMS, and particularly, to accelerometers. This characteristic brings new reliability issues to micromachined accelerometers, including cyclic fatigue cracking of polysilicon cantilevers and springs, mechanical stresses that are caused by packaging and contamination in the internal cavity of the package. Studies of fatigue cracks initiation and growth in polysilicon showed that the fatigue damage may influence MEMS device performance, and the presence of water vapor significantly enhances crack initiation and growth. Environmentally induced failures, particularly, failures due to thermal cycling and mechanical shock are considered as one of major reliability concerns in MEMS. These environmental conditions are also critical for space applications of the parts. For example, the Mars pathfinder mission had experienced 80 mechanical shock events during the pyrotechnic separation processes.

Sharma, Ashok K.↗

NASA NTRS2014

Aeroflex Technology as Class-Y Demonstrator

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Suh, Jong-ook↗

NASA NTRSDate not supplied

Experimental Verification of the Parabolic Deformable Mirror for the ExoSpec Project

For the Habitable Worlds Observatory (HWO), it is essential to broaden the controllable wavelength bandwidth for high-contrast imaging and spectroscopy to increase the exoEarth yield and characterization. The Parabolic Deformable Mirrors (PDM) subpackage, under the NASA Headquarters-directed Exoplanet Spectroscopy (ExoSpec) Work Package, is specifically tailored to do so. We have successfully procured a first-generation (Gen 1) PDM device and completed in-depth characterization of the device. This robust evaluation has become instrumental in informing subsequent stages of development, particularly in shaping the design and specifying requirements for the next generation, Gen 2, PDM device. We have built a testbed in an environmentally controlled cleanroom to experimentally demonstrate the use of a PDM in a coronagraph instrument with an integral field spectrograph (IFS). This versatile testbed is designed to test different DM architectures, low-order wavefront sensing schemes, and a lenslet-based IFS. This provides us with a basis for comparison with different DM configurations: 1) flat DM, 2) PDMs, and 3) a flat DM and PDMs. In this communication, we will discuss the testbed design and updates, PDM characterization, and Gen 2 requirement definitions.

Hari B. Subedi↗

NASA NTRS2016

Single-Event Latchup Testing of the Micrel MIC4424 Dual Power MOSFET Driver

We conducted 47 exposures of four different MIC4424 devices and did not observe any SEL or high-current events. This included worst-case conditions with a LET of 81 MeV-sq cm/mg, applied voltage of 18.5 V, a case temperature greater than 120 C, and a final fluence of 1x10(exp 7)/sq cm. We also monitored both the outputs for the presence of SETs. While the period of the 1 MHz square wave was slightly altered in some cases, no pulses were added or deleted. 1. Purpose: The purpose of this testing is to characterize the BiCMOS/DMOS Micrel MIC4424 dual, non-inverting MOSFET driver for single-event latchup (SEL) susceptibility. These data will be used for flight lot evaluation purposes. 2. Devices Tested: The MIC4423/4424/4425 family are highly reliable BiCMOS/DMOS buffer/driver MOSFET drivers. They are higher output current versions of the MIC4426/4427/4428. They can survive up to 5V of noise spiking, of either polarity, on the ground pin. They can accept, without either damage or logic upset, up to half an amp of reverse current (either polarity) forced back into their outputs. Primarily intended for driving power MOSFETs, the MIC4423/4424/4425 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak currents, and fast switching times. Heavily loaded clock lines, coaxial cables, or piezoelectric transducers are some examples. The only known limitation on loading is that total power dissipated in the driver must be kept within the maximum power dissipation limits of the package. Five (5) parts were provided for SEL testing. We prepared four parts for irradiation and reserved one piece as an un-irradiated control. More information about the devices can be found in Table 1. The parts were prepared for testing by removing the lid from the CDIP package to expose the target die. The parts were then soldered to small copper circuit adapter boards for easy handling. These parts are fabricated in a bulk BiCMOS/DMOS technology. Since we do not know the number of overlayers used in the fabrication processes, linear energy transfer calculations are determined based on the top-surface incident ion species and kinetic energy.

Power MOSFET↗

NASA NTRS2009

On Nibbles and Bytes: The Conundrum of Memory for Space Systems - NASA Electronic Parts and Packaging (NEPP) and Efforts in Memories

Radiation requirements and trends. TID: 1) >90% of NASA applications are < 100 krads-Si in piecepart requirements. a) Many commercial devices (NVM and SDRAMs) meet or come close to this. b) Charge pump TID tolerance has improved an order magnitude over the last 10 years. 2) There are always a few programs with higher level needs and, of course, defense needs SEL: 1) Prefer none or rates that are considered low risk. a) Latent damage is a bear to deal with. 2) As we re packing cells tighter and even with lower Vdd, we re seeing SEL on commercial devices regularly (<90nm). a) Often in power conversion, I/O, or control areas. SEU: 1) It s not the bit errors, it s the SEFIs errors that are the biggest issues. a) Scrubbing concerns for risk, power, speed.

LaBel, Kenneth A.↗

DOE OSTI2023

Validating a Tethered Balloon System and Optical Technologies for Marine Wildlife Detection and Tracking

The interactions between marine wildlife and marine energy devices are not well understood, leading to regulatory delays for device deployments and testing. Technologies that enable marine wildlife observations can help to fill data gaps and reduce uncertainties about animal–device interactions. A validation test conducted in Galveston Bay near La Porte, Texas, in December 2022 used a technology package consisting of a tethered balloon system and three independent sensor systems, including three-band visible, eight-band multispectral, and single-band thermal to detect three marine-mammal-shaped surrogates. The field campaign aimed to provide an initial step to evaluating the use of the TBS and the effectiveness of the sensor suite for marine wildlife observations and detection. From 2 December to 7 December 2022, 6 flights were conducted under varying altitudes and environmental conditions resulting in the collection of 5454 images. A subset of the images was classified and analyzed with two collection criteria including Beaufort wind force scale and TBS altitude to assess a range of observations of a surrogate from near-shore to offshore based on pixel count. The results of this validation test demonstrate the potential for using TBSs and imaging sensors for marine wildlife observations and offer valuable information for further development and application of this technology for marine energy and other blue economy sectors.

47 OTHER INSTRUMENTATION↗

NASA NTRS1976

A high speed imaging system for nuclear diagnostics

A high speed imaging system based on state-of-the-art photosensor arrays was designed for use in nuclear diagnostics. The system is comprised of a front end rapid scan solid state camera, a high speed digitizer, and a PCM line driver in a downhole package and a memory buffer system in an uphole trailer. The downhole camera takes a snapshot of a nuclear device created flux stream, digitizes the image and transmits it to the uphole memory system before being destroyed. The memory system performs two functions: it retains the data for local display and processing by a microprocessor, and it buffers the data for retransmission at slower rates to a computational facility. In the talk, the impetus for such a system as well as its operation was discussed, along with systems under development which incorporate higher data rates and more resolution.

Eyer, H. H.↗

NASA NTRS1987

Development of a P-I-N HgCdTe photomixer for laser heterodyne spectrometry

An improved HgCdTe photomixer technology was demonstrated employing a p-i-n photodiode structure. The i-region was near intrinsic n-type HgCdTe; the n-region was formed by B+ ion implantation; and the p-region was formed either by a shallow Au diffusion or by a Pt Schottky barrier. Experimental devices in a back-side illuminated mesa diode configuration were fabricated, tested, and delivered. The best photomixer was packaged in a 24-hour LN2 dewar along with a cooled GaAs FET preamplifier. Testing was performed by mixing black-body radiation with a CO2 laser beam and measuring the IF signal, noise, and signal-to-noise ratio in the GHz frequency range. Signal bandwidth for this photomixer was 1.3 GHz. The heterodyne NEP was 4.4 x 10 to the -20 W/Hz out to 1 GHz increasing to 8.6 x 10 to the -10 W/Hz at 2 GHz. Other photomixers delivered on this program had heterodyne NEPs at 1 GHz ranging from 8 x 10 to the -20 to 4.4 x 10 to the -19 W/Hz and NEP bandwidths from 2 to 4 GHz.

Bratt, Peter R.↗

NASA NTRS1986

Some design constraints required for the use of generic software in embedded systems: Packages which manage abstract dynamic structures without the need for garbage collection

The embedded systems running real-time applications, for which Ada was designed, require their own mechanisms for the management of dynamically allocated storage. There is a need for packages which manage their own internalo structures to control their deallocation as well, due to the performance implications of garbage collection by the KAPSE. This places a requirement upon the design of generic packages which manage generically structured private types built-up from application-defined input types. These kinds of generic packages should figure greatly in the development of lower-level software such as operating systems, schedulers, controllers, and device driver; and will manage structures such as queues, stacks, link-lists, files, and binary multary (hierarchical) trees. Controlled to prevent inadvertent de-designation of dynamic elements, which is implicit in the assignment operation A study was made of the use of limited private type, in solving the problems of controlling the accumulation of anonymous, detached objects in running systems. The use of deallocator prodecures for run-down of application-defined input types during deallocation operations during satellites.

Johnson, Charles S.↗

NASA NTRS2003

Microelectromechanical System (MEMS) Device Being Developed for Active Cooling and Temperature Control

High-capacity cooling options remain limited for many small-scale applications such as microelectronic components, miniature sensors, and microsystems. A microelectromechanical system (MEMS) using a Stirling thermodynamic cycle to provide cooling or heating directly to a thermally loaded surface is being developed at the NASA Glenn Research Center to meet this need. The device can be used strictly in the cooling mode or can be switched between cooling and heating modes in milliseconds for precise temperature control. Fabrication and assembly employ techniques routinely used in the semiconductor processing industry. Benefits of the MEMS cooler include scalability to fractions of a millimeter, modularity for increased capacity and staging to low temperatures, simple interfaces, limited failure modes, and minimal induced vibration. The MEMS cooler has potential applications across a broad range of industries such as the biomedical, computer, automotive, and aerospace industries. The basic capabilities it provides can be categorized into four key areas: 1) Extended environmental temperature range in harsh environments; 2) Lower operating temperatures for electronics and other components; 3) Precision spatial and temporal thermal control for temperature-sensitive devices; and 4) The enabling of microsystem devices that require active cooling and/or temperature control. The rapidly expanding capabilities of semiconductor processing in general, and microsystems packaging in particular, present a new opportunity to extend Stirling-cycle cooling to the MEMS domain. The comparatively high capacity and efficiency possible with a MEMS Stirling cooler provides a level of active cooling that is impossible at the microscale with current state-of-the-art techniques. The MEMS cooler technology builds on decades of research at Glenn on Stirling-cycle machines, and capitalizes on Glenn s emerging microsystems capabilities.

Beach, Duane E.↗

NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗