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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 469 records · Page 26
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

CEAZ: Accelerating Parallel I/O Via Hardware-Algorithm Co-Designed Adaptive Lossy Compression

As supercomputers continue to grow to exa-scale, the amount of data that needs to be saved or transmitted is exploding. To this end, many previous works have studied using error-bounded lossy compressors to reduce the data size and improve the I/O performance. However, little work has been done for effectively offloading lossy compression onto FPGA-based SmartNICs to reduce the compression overhead. In this paper, we propose a hardware-algorithm co-design of efficient and adaptive lossy compressor for scientific data on FPGAs (called CEAZ) to accelerate parallel I/O. Our contribution is fourfold: (1) We propose an efficient Huffman coding approach that can adaptively update Huffman codewords online based on codewords generated offline (from a variety of representative scientific datasets). (2) We derive a theoretical analysis to support a precise control of compression ratio under an error-bounded compression mode, enabling accurate offline Huffman codewords generation. This also help us create a fixed-ratio compression mode for consistent throughput. (3) We develop an efficient compression pipeline by adopting cuSZ’s dual-quantization algorithm to our hardware use case. (4) We evaluate CEAC on five real-world datasets with both a single FPGA board and 256 nodes from Bridges2 supercomputer. Experiments show that CEAZ outperforms the second-best FPGA-based lossy compressor by 2× of throughput and 9.6× of compression ratio. It also improves MPI_File_write and MPI_Gather throughputs by up to 32.7× and 31.4×, respectively.

Zhang, Chengming↗
DOE OSTI2025

PBE-HIL (Powering the Blue Economy Hardware-in-the-Loop models) [SWR-25-37]

Powering the Blue Economy Hardware-in-the-Loop models (PBE-HIL) is a repository of Power Hardware-in-the-loop models developed for typical Powering the Blue Economy market loads and power requirements. The HIL models were developed to be as generic and functional as possible, meaning that the user can easily configure these models to represent their unique PBE design. These PBE load and power requirement HIL models can then be used to inform marine energy converter (MEC) and power electronics design, as well as be used in laboratory testing using HIL equipment, leading to improved understanding of MEC performance and lower risk prior to open-water MEC deployment.

Labuschagne, Hannes [National Renewable Energy Lab↗
DOE OSTI2026

PCA -BASED COMPRESSOR HARDWARE DESIGN GENERATOR IN CHISEL

SF-25-077 This repository includes a hardware generator written in Chisel that generates lossy compression hardware designs based on principal component analysis (PCA), along with a flexible testbench. It also includes a Python tool for evaluating the accuracy loss of integer quantization.

Kazutomo, Yoshi [Argonne National Laboratory (ANL)↗
DOE OSTI2024

An FPGA-based hardware accelerator supporting sensitive sequence homology filtering with profile hidden Markov models

Abstract Background Sequence alignment lies at the heart of genome sequence annotation. While the BLAST suite of alignment tools has long held an important role in alignment-based sequence database search, greater sensitivity is achieved through the use of profile hidden Markov models (pHMMs). Here, we describe an FPGA hardware accelerator, called HAVAC, that targets a key bottleneck step (SSV) in the analysis pipeline of the popular pHMM alignment tool, HMMER. Results The HAVAC kernel calculates the SSV matrix at 1739 GCUPS on a $$\sim$$ ∼ $3000 Xilinx Alveo U50 FPGA accelerator card, $$\sim$$ ∼ 227× faster than the optimized SSV implementation in nhmmer . Accounting for PCI-e data transfer data processing, HAVAC is 65× faster than nhmmer’s SSV with one thread and 35× faster than nhmmer with four threads, and uses $$\sim$$ ∼ 31% the energy of a traditional high end Intel CPU. Conclusions HAVAC demonstrates the potential offered by FPGA hardware accelerators to produce dramatic speed gains in sequence annotation and related bioinformatics applications. Because these computations are performed on a co-processor, the host CPU remains free to simultaneously compute other aspects of the analysis pipeline.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2025

Microreactor Automated Control System Test Bed Digital Architecture for Real-Time, Hardware-in-the-Loop Simulation

This work describes progress made towards the development of a real-time hardware-in-the-loop (HIL) test bed for non-nuclear testing of microreactor control schemes and failure modes. Non-nuclear testing is a crucial step in developing robust control algorithms for managing microreactor dynamics. The creation of an HIL simulation harnesses the realistic dynamics of physical analogue systems while additionally considering the challenges of variable communication delay. This collaborative effort between Oak Ridge National Laboratory and Idaho National Laboratory has resulted in a LabVIEW-based gRPC communication protocol which couples a TRANSFORM Modelica simulation of nuclear components to the ViBRANT physical hardware for realistic feedback and visual representation of control action in real time. A modular python client structure is developed to manage FMU-based Modelica simulation and real-time gRPC communication. HIL testing suggests that the modeled reactor with natural convection molten salt loop coolant configuration responds well to PID control of drum positioning for modulation of reactor core power, however, future efforts will be made to explore the added thermal inertial delay of system level control and downstream demand changes. Development of this platform with a generalized methodology provides a foundation for exploring a variety of reactor configurations and failure modes in rapid order to provide insight into the most effective avenues of study for further research and development.

McConnell, Jono [ORNL] (ORCID:0000000238984741)↗
DOE OSTI2024

Strategic styles of hardware product development could accelerate commercialization in cleantech startups

Hardware-based startups risk having longer times-to-market, deterring investment in the clean technologies that are critical to a sustainable future. We interviewed 55 leaders at hardware startups, 20 of which are cleantech, mapped their development timelines, and found prototyping to be the longest development step (median of 19 weeks per prototype) regardless of prototype complexity or iteration. Qualitative interview analysis reveals the prototyping team’s choice of development style is a major factor affecting timeline. We define two development styles: natural and structured, typified by free-form exploration and rule-based execution, respectively. On average, natural development takes 35% less time than structured, and is thus preferred for early iterations, but adopting structure at strategic points is needed for timely commercialization. Critical points of transition to a structured style include adding new team members or engaging external partners, which demand clear communication and expectations. When pivoting to a new product or market, returning to a natural style is beneficial.

Looney, Erin (ORCID:0000000168959312)↗
DOE OSTI2021

Hardware-In-the-Loop Benchmarking Setup for Phasor Based Control Validation

Phasor Based Control is a novel approach to controlling Distributed Energy Resources that aims at relieving various constraints that arise in the distribution grid. It is a two-layer control system with a supervisory control that coordinates distributed controllers to reach voltage phasor targets. The distributed controllers use local synchrophasor measurements and operate as feedback controllers. This control method is currently under development with several algorithms being under consideration for both the central and ditributed components. In this paper, we present the experimental setup that was prepared to prototype a hardware implementation and validate the control method in Hardware-In-the-Loop.

Baudette, Maxime↗
DOE OSTI2012

Benchmarking Non-Hardware Balance-of-System (Soft) Costs for U.S. Photovoltaic Systems Using a Bottom-Up Approach and Installer Survey

This report presents results from the first U.S. Department of Energy (DOE) sponsored, bottom-up data-collection and analysis of non-hardware balance-of-system costs—often referred to as “business process” or “soft” costs—for residential and commercial photovoltaic (PV) systems. Annual expenditure and labor-hour-productivity data are analyzed to benchmark 2010 soft costs related to the DOE priority areas of (1) customer acquisition; (2) permitting, inspection, and interconnection; (3) installation labor; and (4) installer labor for arranging third-party financing. Annual expenditure and labor-hour data were collected from 87 PV installers. After eliminating outliers, the survey sample consists of 75 installers, representing approximately 13% of all residential PV installations and 4% of all commercial installations added in 2010. Including assumed permitting fees, in 2010 the average soft costs benchmarked in this analysis total $1.50/W for residential systems (ranging from $0.66/W to $1.66/W between the 20th and 80th percentiles). For commercial systems, the median 2010 benchmarked soft costs (including assumed permitting fees) are $0.99/W for systems smaller than 250 kW (ranging from $0.51/W to $1.45/W between the 20th and 80th percentiles) and $0.25/W for systems larger than 250 kW (ranging from $0.17/W to $0.78/W between the 20th and 80th percentiles). Additional soft costs not benchmarked in the present analysis (e.g., installer profit, overhead, financing, and contracting) are significant and would add to these figures. The survey results provide a benchmark for measuring—and helping to accelerate—progress over the next decade toward achieving the DOE SunShot Initiative’s soft-cost-reduction targets. We conclude that the selected non-hardware business processes add considerable cost to U.S. PV systems, constituting 23% of residential PV system price, 17% of small commercial system price, and 5% of large commercial system price (in 2010). These processes present significant opportunities for further cost reductions and labor-productivity gains.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2015

Enabling Exascale Hardware and Software Design through Scalable System Virtualization (Final Report)

The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems software for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3), although a prototype connecting Palacios with the GEM5 architectural simulator was demonstrated, our conclusion was that such a platform was less useful for design space exploration than anticipated due to inherent complexity of the connection between the instruction set architecture level and the microarchitectural level. For effort (4), we found that a code injection approach proved to be more fruitful. The results of our efforts are publicly available in the open source Palacios codebase and published papers, all of which are available from the project web site, v3vee.org. Palacios is currently one of the two codebases (the other being Sandia’s Kitten lightweight kernel) that underlies the node operating system for the DOE Hobbes Project, one of two projects tasked with building a systems software prototype for the national exascale computing effort.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

15 MW HArdware-in-the-loop Grid Simulation Project

The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA hardware that allows for communication between the key real-time interfaces and reduces the latency between these interfaces to acceptable levels for HIL experiments.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2018

Blackcomb 2: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

Fast non-volatile memory (NVM) offers game-changing opportunities to rethink traditional system architectures; to address their energy inefficiencies; to leverage the new devices for greater performance; and to exploit the new capability of non-volatility to enhance system resilience, even in the face of larger system scale and degraded reliability of components. However, the devil is in the details, and to reap such potential benefits we must address challenges that arise when the contents of memory survive application failure, when software becomes responsible for managing the contents of CPU caches, and when memory accelerators blur the line between hardware and software. Building on the accomplishments of the Blackcomb Project, funded in 2010, we have identified, evaluated, and optimized promising NVM hardware and software technologies that are essential to provide the necessary memory capacity, performance, resilience, and energy efficiency in exascale systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

ZFP Hardware Implementation

As core counts increase in new HPC systems with comparatively little increase in memory bandwidth, the trend is an effective decrease in memory bandwidth per core. Other bandwidth limitations in HPC systems exist between CPU and GPU memory, between system nodes, and between node memory and storage. Compression of floating-point data has the potential to reduce data movement and pressure across these communication channels. Furthermore, it has the potential to reduce the footprint of floating-point arrays stored in memory. ZFP, implemented in software, is gaining traction as an effective method in floating-point compression; however, performance gains are limited to the spare compute cycles available before reaching the bandwidth limitations of the communication channel. A hardware implementation of ZFP has the potential to raise the bar on performance. From the inception of ZFP, it was designed to accommodate a hardware implementation.

42 ENGINEERING↗
DOE OSTI2022

The Importance of Scientific Visualization on Novel Hardware

Innovation in HPC hardware and adoption of heterogeneous systems has led to a variety of unique programming models. This has led to a challenge for scientific visualization software (and indeed all HPC software) to take full advantage of recent generations of supercomputing. Edge computing, where hardware is specialized for the needs of the particular application, exacerbates the problem. VTK-m has had many successes on this front by providing device-agnostic algorithms that compare favorably to implementations written to specific devices as shown in Table 1. However, VTK-m has focused mostly on GPU and traditional CPU multicore technology. There are numerous processor technologies, both existing and potential future, that are not being addressed by current R&D efforts.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Evaluation of the Feasibility of Utilizing a Low-Cost UWB Radar for Hardware Implant & Counterfeit Device Detection

Hardware implants & counterfeit devices in the US power grid pose a significant national security threat. Asset owners currently have few options for detecting the presence of such devices “in the wild”. The goal of this work is to develop a non-invasive sensing method to solve this problem. In this work we evaluate the feasibility of implementing a nonlinear UWB radar tomography system to differentiate between electronic internals of externally-similar devices using low-cost off-the-shelf hardware.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Hardware-in-the-loop Testing of Network Protectors for Low-Voltage Networks with Distributed Energy Resources

In this report, we developed and validated a network protector relay digital twin model and interfaced a commonly used network protector relay hardware with our real-time simulation system. Hardware-in-the-loop protection studies are performed to assess the impact of distributed energy resources (DER) and benchmark a rate-of-change-based mitigation strategy. Simulation results suggest that the network protector reverse trip and auto-reclose functions are negatively impacted by the high distributed energy resource penetration. To accommodate DER backfeed while remaining secure and reliable for faults on primary feeders, we recommend options for a rate-of-change-based blocking scheme and a protection setting change. Finally, future mitigation ideas and standard revisions are discussed.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Hardware Specification and Reference Design for the Low-Cost, Interoperable, User-Centric, Supervisory Controller Kit for Small and Medium Size Commercial Buildings

Commercial buildings are responsible for approximately 20 percent of the total United States energy consumption and greenhouse gas emissions. Over 85 percent of these buildings lack building automation systems to manage the various building systems they have. Many of these buildings are small (< 50,000 square feet), underserved, and use rooftop units (RTUs) for heating, ventilation, and air-conditioning needs. Because these buildings lack proper control systems, they have several operational deficiencies that lead to excess energy consumption. Studies have shown that managing the RTU’s heating and cooling setpoints, schedules, setbacks, and optimal start times can result in 20 to 25 percent reduction in electricity consumption in small and medium commercial buildings (SMBs). In addition, improving the demand flexibility of these buildings will result in additional cost savings for the building owner. To address the needs of the SMBs, the Department of Energy’s Building Technologies Office jointly funded Pacific Northwest National Laboratory (PNNL) and Oak Ridge National Laboratory (ORNL) to design, develop, test, and validate a low-cost, interoperable, user-centric, retrofit supervisory controller kit (SC-SMB) that can be used to continuously optimize energy consumption and deliver demand flexibility of SMBs, including all-electric buildings, and provide a means for maximizing decarbonization benefits. The team also includes industry partners Edo and Intellimation. Previously, the team drafted an SC-SMB system specification document (Goodman et al. 2023). This document describes a reference design of a low-cost supervisory control system for SMBs, including the various hardware components, software system, and an example implementation of the reference design. The final release of the reference design is planned for December 2025. Section 2.0 of the report documents the relevant building types that the SC-SMB system is suitable for. Section 3.0 documents the various hardware components, their function, cost, whether they are off-the-shelve, support standard communication, etc., and the software system. An example deployment in a 10,000-sf building with six rooftop units, a hot water heater, solar, and storage is described in Section 4.0. The planned next steps are described in Section 5.0, and references are listed in Section 6.0.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2025

A Scalable Hardware-and-Human-in-the-Loop Grid-interactive Efficient Building Equipment Performance Dataset

This project developed a publicly available, high-fidelity dataset about the interactions among humans, homes, and heat pumps supporting grid interactive efficient buildings to balance demand on the grid with comfort for occupants. Laboratory measurements and simulations of the hardware capture the second-scale electric power dynamics of heat pumps providing grid services like load shifting and load shedding. Field measurements, behavior tracking, and qualitative surveys of people in their homes over multiple years—including experimentally adjusting the heating and cooling system to provide grid services—to capture the reciprocal effect of human behavior on grid services, and grid services on human comfort. Taken together, these data capture the complete Hardware and Human in the loop system for residential heat pumps, reducing large uncertainties in simulation for design, and models for control of heat pumps, and grid-interactive buildings.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2026

Use of Hardware-in-the-Loop to De-Risk Field Deployment of Hydrogen Assets

Grid-forming assets are required in microgrids to act as voltage-frequency masters. These grid-forming assets can operate in two modes of operation: grid-following mode and grid-forming mode. In grid-following mode of operation, these assets will follow real power and reactive power setpoints and in grid-forming mode of operation these assets will follow voltage and frequency setpoints. Traditionally, diesel generators or natural gas-based generators are widely used to act as a voltage-frequency master. However, many utilities are aiming to replace generators with grid forming-inverters supplied by solar photovoltaics (PV), batteries or fuel cells. Since grid-forming assets need a long-term reliable energy source, fuel cells are a reasonable and viable choice to supply the grid-forming inverters, but some of the challenges facing the wide deployment of grid-forming fuel cell inverters need to be addressed. Specifically, in our proposed work, we aim to focus on the interconnection and interoperability requirements of grid-forming fuel cell inverters. Currently, state-of-the-art fuel cell inverters follow the general interconnection requirements of distributed energy resources (DERs) and general interoperability requirements of DERs, but these requirements were built with PV and battery systems in mind. Fuel cells have different operational requirements, and therefore these requirements need to be appropriately modified for the grid operators to use. These additional steps add to the investment and operational cost to the grid operators. Through the ARIES platform, this proposed project aims to bridge this gap and use power hardware-in-the-loop (PHIL) and controller hardware-in-the-loop (CHIL) experiments to inform the creation of open-source interconnection and interoperability information that can aid in faster and cheaper installation and operation of grid-forming fuel cell inverters.

08 HYDROGEN↗