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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 469 records · Page 26
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Light-detection electronics for a Raman lidar

A light-detection system for an optical radar, or lidar, unit to be used for remote temperature and composition measurements was designed, built, and bench tested. This detection system processes three return signal wavelengths: two Raman wavelengths, and the Rayleigh-Mie wavelength at 694.3 nanometers. Means of coping with photomultiplier tube instabilities and limitations are discussed. Circuits for gain control, ranging, and digitizing are included. The phototube gains can be switched fully on in 80 meters (450 nsec) or off in 30 meters (200 nsec) of range. The range circuit processes signals from 0.1 to 2 kilometers, with an estimated range resolution of less than 5 meters.

Leser, R. J.↗
DOE OSTI2023

Realizing symmetry-protected topological phases in a spin-1/2 chain with next-nearest-neighbor hopping on superconducting qubits

Quantum simulation on near-term quantum hardware is a topic of intense interest. The preparation of novel quantum states of matter provides a quantitative assessment of the capabilities of near-term digital quantum computers to implement circuits with structure of relevance to quantum simulation. Here, we conduct a benchmark study by realizing symmetry-protected topological (SPT) phases of a spin-1/2 Hamiltonian with next-nearest-neighbor hopping on up to 11 qubits on a programmable superconducting quantum processor using adiabatic state preparation. Using recompilation techniques to reduce the gate count to around 50 two-qubit gates, we observe clear signatures of the two distinct SPT phases, such as excitations localized to specific edges and finite string-order parameters. Finally, we identify a parasitic phase associated with the two-qubit gate as the dominant imperfection that limits the depth of the circuits, indicating a research topic of interest for future hardware development.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Promise of Graph Sparsification and Decomposition for Noise Reduction in QAOA: Analysis for Trapped-Ion Compilations

We develop new approximate compilation schemes that significantly reduce the expense of compiling the Quantum Approximate Optimization Algorithm (QAOA) for solving the Max-Cut problem. Our main focus is on compilation with trapped-ion simulators using Pauli-X operations and all-to-all Ising Hamiltonian HIsing evolution generated by Molmer-Sorensen or optical dipole force interactions, though some of our results also apply to standard gate-based compilations. Our results are based on principles of graph sparsification and decomposition; the former reduces the number of edges in a graph while maintaining its cut structure, while the latter breaks a weighted graph into a small number of unweighted graphs. Though these techniques have been used as heuristics in various hybrid quantum algorithms, there have been no guarantees on their performance, to the best of our knowledge. This work provides the first provable guarantees using sparsification and decomposition to improve quantum noise resilience and reduce quantum circuit complexity. For quantum hardware that uses edge-by-edge QAOA compilations, sparsification leads to a direct reduction in circuit complexity. For trapped-ion quantum simulators implementing all-to-all HIsing pulses, we show that for a (1−ϵ) factor loss in the Max-Cut approximation (ϵ>0), our compilations improve the (worst-case) number of HIsing pulses from O(n2) to O(nlog(n/ϵ)) and the (worst-case) number of Pauli-X bit flips from O(n2) to O(nlog(n/ϵ)ϵ2) for n-node graphs. This is an asymptotic improvement for any constant ϵ>0. We demonstrate that significant improvements to the approximation ratio are obtained using decomposition in simulated trapped-ion experiments with dephasing noise. We further present a generic argument showing that sparsification results in an exponentially improved circuit fidelity lower bound in digital computing schemes based on one- and two-qubit gates, which are relevant to a wide variety of hardwares such as superconducting qubits and certain neutral atom or trapped ion setups, and more sophisticated noise models. We anticipate these approximate compilation techniques will be useful tools in a variety of future quantum computing experiments.

Moondra, Jai [Georgia Institute of Technology]↗
NASA NTRS1964

Digital cardiometer computes and displays heartbeat rate

To compute the heartbeat rate from the waveform output of an electrocardiogram, a digital cardiometer with solid state circuit elements has been developed. This computes the beat every 15 seconds and visually presents the data on numerical display tubes.

Mitchell, V. M.↗
NASA NTRS1968

Two-way digital driver/receiver uses one set of lines

Two-way /bilateral/ digital driver/receiver system using MOS circuits was designed for a multiprocess computer having several subsystems at relatively close locations. The system requires only a single set of communication lines between subsystems, thus achieving lower cost with increased reliability.

Burnett, G. J.↗
NASA NTRS1972

Third order digital-to-analog converter

System, consisting of sample and hold digital-to-analog converter, clock circuit, sample delay circuit, initial condition circuit and interpolator circuit, improves accuracy of reconstructed analog signal without increasing sample rates.

Dotson, W. P.↗
NASA NTRS1979

Fader and ramp shaper replace linear filters

Digital "fader" or "ramp shaper" circuits replace linear filters in suppressing switching transients and instabilities within servocontrol systems. Circuits can be optimized to introduce no attenuation, transport delay, or phase lags in new output signal.

Robinson, T. A.↗
NASA NTRS1979

Computation-saving digital filter

Two stage digital low-pass filter circuit that averages input over given period and filters average over comparatively slow rate, reduces computation, speed, and word-length requirements. Applications include data preprocessing before entry to central processor.

Sowada, D. J.↗
NASA NTRS1978

Contour Detector and Data Acquisition System for the Left Ventricular Outline

A real-time contour detector and data acquisition system is described for an angiographic apparatus having a video scanner for converting an X-ray image of a structure characterized by a change in brightness level compared with its surrounding into video format and displaying the X-ray image in recurring video fields. The real-time contour detector and data acqusition system includes track and hold circuits; a reference level analog computer circuit; an analog compartor; a digital processor; a field memory; and a computer interface.

Reiber, J. H. C.↗
NASA NTRS1991

Programmable Maintenance Processor For XAIDS

Programmable maintenance processor (MAINT) made of commercially available integrated circuits. Autonomous one of four digital electronic processors in extended aircraft interrogation and display system (XAIDS). Developed for testing of system and application computer programs as well as for testing equipment. MAINT has independent terminal and printer interfaces and dedicated magnetic bubble memory storing system-testing sequences entered from terminal. Software for MAINT written in PLM86 programming language and broken into four separate modules.

Glover, Richard↗
NASA NTRS1992

A radial basis function neurocomputer implemented with analog VLSI circuits

An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

Watkins, Steven S.↗
NASA NTRS1991

SPROC: A multiple-processor DSP IC

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Davis, R.↗
NASA NTRS2009

NASA Tech Briefs, September 2009

opics covered include: Filtering Water by Use of Ultrasonically Vibrated Nanotubes; Computer Code for Nanostructure Simulation; Functionalizing CNTs for Making Epoxy/CNT Composites; Improvements in Production of Single-Walled Carbon Nanotubes; Progress Toward Sequestering Carbon Nanotubes in PmPV; Two-Stage Variable Sample-Rate Conversion System; Estimating Transmitted-Signal Phase Variations for Uplink Array Antennas; Board Saver for Use with Developmental FPGAs; Circuit for Driving Piezoelectric Transducers; Digital Synchronizer without Metastability; Compact, Low-Overhead, MIL-STD-1553B Controller; Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM; Differential InP HEMT MMIC Amplifiers Embedded in Waveguides; Improved Aerogel Vacuum Thermal Insulation; Fluoroester Co-Solvents for Low-Temperature Li+ Cells; Using Volcanic Ash to Remove Dissolved Uranium and Lead; High-Efficiency Artificial Photosynthesis Using a Novel Alkaline Membrane Cell; Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays; Micro-Horn Arrays for Ultrasonic Impedance Matching; Improved Controller for a Three-Axis Piezoelectric Stage; Nano-Pervaporation Membrane with Heat Exchanger Generates Medical-Grade Water; Micro-Organ Devices; Nonlinear Thermal Compensators for WGM Resonators; Dynamic Self-Locking of an OEO Containing a VCSEL; Internal Water Vapor Photoacoustic Calibration; Mid-Infrared Reflectance Imaging of Thermal-Barrier Coatings; Improving the Visible and Infrared Contrast Ratio of Microshutter Arrays; Improved Scanners for Microscopic Hyperspectral Imaging; Rate-Compatible LDPC Codes with Linear Minimum Distance; PrimeSupplier Cross-Program Impact Analysis and Supplier Stability Indicator Simulation Model; Integrated Planning for Telepresence With Time Delays; Minimizing Input-to-Output Latency in Virtual Environment; Battery Cell Voltage Sensing and Balancing Using Addressable Transformers; Gaussian and Lognormal Models of Hurricane Gust Factors; Simulation of Attitude and Trajectory Dynamics and Control of Multiple Spacecraft; Integrated Modeling of Spacecraft Touch-and-Go Sampling; Spacecraft Station-Keeping Trajectory and Mission Design Tools; Efficient Model-Based Diagnosis Engine; and DSN Simulator.

Source record↗
NASA NTRS2010

System on a Chip (SoC) Overview

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

LaBel, Kenneth A.↗
NASA NTRS2003

Modular, Parallel Pulse-Shaping Filter Architectures

Novel architectures based on parallel subconvolution frequency-domain filtering methods have been developed for modular processing rate reduction of discrete-time pulse-shaping filters. Such pulse-shaping is desirable and often necessary to obtain bandwidth efficiency in very-high-rate wireless communications systems. In principle, this processing could be implemented in very-large-scale integrated (VLSI) circuits. Whereas other approaches to digital pulse-shaping are based primarily on time-domain processing concepts, the theory and design rules of the architectures presented here are founded on frequency-domain processing that has advantages in certain systems.

Gray, Andrew A.↗