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At least 469 records · Page 26
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Detector thickness effects on nanosecond-gated imager response

Hybrid CMOS multi-frame imagers with exposure times down to ~2 ns have made significant impacts in high energy density physics and inertial confinement fusion research. The detector thickness is a key parameter in both detector quantum efficiency and temporal response. The Icarus hybrid CMOS imager has been fabricated with Si detector thicknesses of 8, 25, and 100 µm. The temporal response of imaging sensors with exposure time down to 2 ns has been examined and compared to directly measured photodiode current. The 100-μm thick variant displays extended features related to charge carrier collection and is more susceptible to field collapse. Here, we also demonstrate charge collection time effects on spatial response.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Thermally generated magnonic spin currents in a polycrystalline gadolinium iron garnet thin film with perpendicular magnetic anisotropy

Rare-earth iron garnets (REIGs) are the benchmark systems for magnonics, including the longitudinal spin Seebeck effect (LSSE). While most research has focused on single-crystalline REIGs on complimentary garnet substrates, moving to more, cost-effective complementary metal-oxide semiconductor (CMOS)-compatible substrates is important to integrate REIG thin films with existing technology. In this regard, we grow a 130 nm-thick polycrystalline gadolinium iron garnet (GdIG) film on the Si/SiO2 substrate and investigate the temperature-dependent LSSE. Interestingly, the polycrystalline GdIG film exhibits perpendicular magnetic anisotropy (PMA) at room temperature which is induced by tensile in-plane (IP)-strain originating from the thermal-expansion mismatch between the GdIG film and the substrate during rapid thermal annealing. Further, a spin-reorientation transition from the out-of-plane IP direction below TS = 180 K is observed. Additionally, the film reveals a magnetic compensation temperature, TComp, of ≈240 K. The LSSE voltage not only demonstrates a sign-inversion around TComp, but also shows noticeable changes around TS. As compared to a single-crystalline GdIG film, the lower LSSE voltage for the polycrystalline GdIG is attributed to the higher effective magnetic anisotropy and enhanced magnon scattering at the grain boundaries. Our study not only paves the way for the cost-effective growth of CMOS-compatible REIG-based systems with PMA for magnonic memory and information processing applications, but also highlights the fact that the spincaloritronic and spin-insulatronic properties of the polycrystalline REIGs follow those of their single-crystalline counterparts with reduced spin-to-charge conversion efficiency through LSSE which can be tuned further by controlling the average gran size and interface engineering.

Physics↗
DOE OSTI2025

Perspectives of active Si photonics devices for data communication and optical sensing

Si photonics has made rapid progress in research and commercialization in the past two decades. While it started with electronic–photonic integration on Si to overcome the interconnect bottleneck in data communications, Si photonics has now greatly expanded into optical sensing, light detection and ranging (LiDAR), optical computing, and microwave/RF photonics applications. From an applied physics point of view, this perspective discusses novel materials and integration schemes of active Si photonics devices for a broad range of applications in data communications, spectrally extended complementary metal–oxide–semiconductor (CMOS) image sensing, as well as 3D imaging for LiDAR systems. We also present a brief outlook of future synergy between Si photonic integrated circuits and Si CMOS image sensors toward ultrahigh capacity optical I/O, ultrafast imaging systems, and ultrahigh sensitivity lab-on-chip molecular biosensing.

electronic band structure↗
DOE OSTI2024

Magnetic tunnel junction random number generators applied to dynamically tuned probability trees driven by spin orbit torque

Abstract Perpendicular magnetic tunnel junction (pMTJ)-based true-random number generators (RNGs) can consume orders of magnitude less energy per bit than CMOS pseudo-RNGs. Here, we numerically investigate with a macrospin Landau–Lifshitz-Gilbert equation solver the use of pMTJs driven by spin–orbit torque to directly sample numbers from arbitrary probability distributions with the help of a tunable probability tree. The tree operates by dynamically biasing sequences of pMTJ relaxation events, called ‘coinflips’, via an additional applied spin-transfer-torque current. Specifically, using a single, ideal pMTJ device we successfully draw integer samples on the interval [0, 255] from an exponential distribution based on p -value distribution analysis. In order to investigate device-to-device variations, the thermal stability of the pMTJs are varied based on manufactured device data. It is found that while repeatedly using a varied device inhibits ability to recover the probability distribution, the device variations average out when considering the entire set of devices as a ‘bucket’ to agnostically draw random numbers from. Further, it is noted that the device variations most significantly impact the highest level of the probability tree, with diminishing errors at lower levels. The devices are then used to draw both uniformly and exponentially distributed numbers for the Monte Carlo computation of a problem from particle transport, showing excellent data fit with the analytical solution. Finally, the devices are benchmarked against CMOS and memristor RNGs, showing faster bit generation and significantly lower energy use.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Toward ultrafast, ultra-stable imaging arrays: Superlattice doping to enhance the performance of backside-illuminated 3D-hybridized silicon photodetectors

In this paper, the authors report the latest results on their development of superlattice-doped, thinned, backside-illuminated (BSI), 3D-integrated photodiode detectors—a step toward their ultimate goal of demonstrating ultrafast, ultrastable CMOS imaging arrays. As with most silicon-based photodetectors, backside-illumination and backside surface passivation are keys to achieve the highest performance capability. The two-dimensional (2D) doping technique developed at the Jet Propulsion Laboratory (JPL) has proved to result in a highly efficient, highly stable detector response when combined with a variety of detectors. Here, JPL's 2D-doping has been combined with Sandia's BSI photodetectors hybridized with custom fanout wafer via copper Direct Bond Interconnect (DBI®), a technology that is rapidly becoming industry standard for BSI CMOS imaging arrays. The prototype detectors were packaged and evaluated with respect to their response to low energy electrons. The authors find that the responsivity of 2D-doped BSI detectors is higher than devices prepared using other surface passivation techniques (i.e., ion implantation). The success of the work described herein verifies that the 2D-doping processes previously developed for Sandia's frontside-illuminated photodetectors are generally applicable to BSI detectors and demonstrates for the first time that JPL's 2D-doping process is compatible with the Cu-DBI® technology.

Jewell, April D.↗
DOE OSTI2020

A heterogeneously integrated silicon photonic/lithium niobate travelling wave electro-optic modulator

Silicon photonics is a platform that enables densely integrated photonic components and systems and integration with electronic circuits. Depletion mode modulators designed on this platform suffer from a fundamental frequency response limit due to the mobility of carriers in silicon. Lithium niobate-based modulators have demonstrated high performance, but the material is difficult to process and cannot be easily integrated with other photonic components and electronics. In this manuscript, we simultaneously take advantage of the benefits of silicon photonics and the Pockels effect in lithium niobate by heterogeneously integrating silicon photonic-integrated circuits with thin-film lithium niobate samples. We demonstrate the most CMOS-compatible thin-film lithium niobate modulator to date, which has electro-optic 3 dB bandwidths of 30.6 GHz and half-wave voltages of 6.7 V×cm. These modulators are fabricated entirely in CMOS facilities, with the exception of the bonding of a thin-film lithium niobate sample post fabrication, and require no etching of lithium niobate.

42 ENGINEERING↗
DOE OSTI2020

Chirped-grating spectrometer-on-a-chip

We demonstrate an on-chip spectrometer readily integrable with CMOS electronics. The structure is comprised of a SiO 2 /Si 3 N 4 /SiO 2 waveguide atop a silicon substrate. A transversely chirped grating is fabricated, in a single-step optical lithography process, on a portion of the waveguide to provide angle and wavelength dependent coupling to the guided mode. The spectral and angular information is encoded in the spatial dependence of the grating period. A uniform pitch grating area, separated from the collection area by an unpatterned propagation region, provides the out-coupling to a CMOS detector array. A resolution of 0.3 nm at 633 nm with a spectral coverage tunable across the visible and NIR (to ∼ 1 µm limited by the Si photodetector) by changing the angle of incidence, is demonstrated without the need for any signal processing deconvolution. This on-chip spectrometer concept will cost effectively enable a broad range of applications that are beyond the reach of current integrated spectroscopic technologies.

Nezhadbadeh, Shima↗
DOE OSTI2023

Realization of a wide steering end-fire facet optical phased array using silicon rich silicon nitride

The design, fabrication, and characterization of a 16-element optical phased array (OPA) using a high index (n = 3.1) silicon-rich silicon nitride (SRN) is demonstrated. Here, we present one-dimensional beam steering with end-fire facet antennas over a wide steering range of >115° at a fixed wavelength of 1525 nm. A beam width of 6.3° has been measured at boresight, consistent with theory. We demonstrate SRN as a viable material choice for chip-scale OPA applications due to its high thermo-optic coefficient, high optical power handling capacity [negligible two-photon absorption (TPA)], wide transparency window, and CMOS compatibility.

Nejadriahi, Hani↗
DOE OSTI2021

Hybrid integrated photonic platforms: opinion

While photonic integration has made remarkable progress in recent years, there is no one integrated photonic platform that offers all desired functionalities and manufacturability on the same platform. GaAs and InP-based optoelectronic integrated circuits (OEICs) were very popular in the past decades; however, silicon photonics has recently emerged as a preferred platform due to its high-density and high-yield manufacturability leveraging the CMOS ecosystem, although it lacks optical gain, the Pockels effect, and other characteristics. On the other hand, hybrid photonic integration adds new and diverse functionalities to the host materials like silicon. This opinion paper investigates hybrid integrated photonic platforms, and discusses the new functionalities added to the silicon CMOS photonic platform.

42 ENGINEERING↗
DOE OSTI2023

Photon-to-Digital Converters for Neutron Imaging Instruments (Final Report)

Oak Ridge National Laboratory (ORNL) collaborated with the Université de Sherbrooke (UdeS) to design a modular and scalable tile of innovative digital photodetectors called Photon-to-Digital Converters (PDC) and the required subsystems to demonstrate the feasibility of large area single-photon detectors to support high-resolution, depth-of-interaction, fast neutron radiography based on scintillation detectors. The goal is to demonstrate the advantages of using PDC over conventional Silicon Photomultiplier (SiPM) for neutron imaging systems. The basic building blocks of analog SiPM and PDC are Single-Photon Avalanche Photodiodes (SPAD). The main difference between conventional SiPMs and PDCs, is in the fact that analog SiPMs sum the charge produced by individual SPAD passively, while in PDCs each SPAD is read out individually by an active electronic circuit. Hence, PDCs provide a direct photon-to-bit conversion where a logic “1” means that there was a detection in a given SPAD. Conversely, an analog SiPM requires a sophisticated preamplifier (current amplifiers or transimpedance amplifier) followed by a shaping amplifier and an analog-to-digital converter. Moreover, since the charge from each SPAD varies slightly, the passive sum of the analog SiPM will have signal fluctuations for the same amount of photon detected. This is one of many issues that is completely eliminated by individual one-to-one SPAD read out in PDCs. The large area required for scintillator readouts for neutron imaging is such that the output capacitance of a large area of SiPM arrays is very high. This creates a burden on the signal-to-noise optimization with respect to the power budget. For PDC, the power consumption is dictated by rate of the incident photon flux, or in photon-starved environments, the dark noise rate of the SPAD array. In other words, the power consumption in the absence of events is extremely low. Hence, the power consumption of a PDC read out system is much lower than its analog counterpart. Further, the large SiPM capacitance may introduce signal distortions on the scintillator fast rise or decay time with undesired effects on timing and pulse shape discrimination. The problem is absent in PDCs, as their readout is independent on device capacitance. UdeS is the world leader in 3D vertical integration of frontside illuminated SPAD arrays over CMOS readouts. These capabilities allow future production of “3D PDC” with maximum photosensitive fill factor and electronic functionalities tailored to the application. UdeS' vast knowledge of SPADs and CMOS design made the team an ideal collaborator in the development of large area high-resolution fast neutron radiography.

42 ENGINEERING↗
DOE OSTI2024

Development of selenium imaging detectors toward a definitive search for neutrinoless ββ decay

Imaging sensors made from an ionization target layer of amorphous selenium (aSe) coupled to a silicon complementary metal-oxide-semiconductor (CMOS) active pixel array for charge readout are a promising technology for neutrino physics. The high spatial resolution in a solid-state target provides unparalleled rejection of backgrounds from natural radioactivity in the search for the neutrinoless ββ decay of 82 Se. With this grant, we experimentally determined two crucial factors necessary for the realization of this novel technology: i) the intrinsic energy response of aSe to ionizing electrons, and ii) the feasibility to couple a target layer of aSe to a CMOS active pixel sensor to image electron tracks.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Performance of the AstroPix Prototype Module for the Barrel Imaging Calorimeter at the ePIC Detector and in Space-Based Payloads

AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.

Kim, Bobae (ORCID:0000000295396815)↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1974

Airoscope command system

A PCM telemetry command system is presented having a capacity of 256 unique commands, an end-to-end actuation time of less than 250 milliseconds, and an address plus complementary command code to provide security against the acceptance of anything but intended commands. The system consists of a ground-based encoder and a balloon-borne decoder, both built using low-current drain, high reliability CMOS logic elements. Commands are normally issued by a simple switch closure to +5VDC on the appropriate input line, however as a backup mode, the 8-bit command may be entered manually on 8 toggle switches and executed via a SEND button. In any case, the command is then serialized into a PCM bit stream and sent via a P-Band radio link to the DECODER aloft. All 256 outputs from the DECODER are buffered through drivers and thus may be used to drive CMOS, TTL, or DTL logic.

Barrows, W.↗
NASA NTRS1975

Hardening of MJS77 spacecraft against the Jupiter radiation belts

Results of the device characterization program to identify components of the Mariner Jupiter/Saturn spacecraft in need of radiation hardening to meet a total dose requirement of 5 trillion e/sq cm are presented. The parts to be tested, including bipolar transistors, JFETs, SCRs, CMOS devices, linear integrated circuits, Zener diodes and other radiation-sensitive parts, were identified by a worst case circuit analysis of the 20 major subsystems. The test samples were exposed to several levels of irradiation from a Dynamitron electron accelerator capable of producing a steady stream of electrons at energies up to 2.5 eV. The electrical parameters of the devices were measured immediately following irradiation to prevent annealing. CMOS devices and linear devices showed the most severe degradation in a moderate radiation environment, and significant degradation was produced at low current in bipolar transistors. Three methods used for screening a number of devices determined by circuit and shielding analyses to be unacceptable radiation-sensitive are described: diffusion and metallization lot screening; wafer lot screening; and irradiation-anneal screening.

W E Price↗
NASA NTRS1977

Sensing circuits for multiwire proportional chambers

Integrated sensing circuits were designed, fabricated, and packaged for use in determining the direction and fluence of ionizing radiation passing through a multiwire proportional chamber. CMOS on sapphire was selected because of its high speed and low power capabilities. The design of the proposed circuits is described and the results of computer simulations are presented. The fabrication processes for the CMOS on sapphire sensing circuits and hybrid substrates are outlined. Several design options are described and the cost implications of each discussed. To be most effective, each chip should handle not more than 32 inputs, and should be mounted on its own hybrid substrate.

Peterson, H. T.↗
NASA NTRS1980

11-Line to 512-line decoder

CMOS decoder is assembled from standard 4-line to 16-line decoder/demultiplexer IC's. Matrix may also be used to generate 256 latched-on or latched-off logic signals instead of 512 discrete unlatched signals. By using conventional CMOS IC's, circuit consumes only about 30 milliwatts.

Miller, W. N.↗