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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps.

Routh, D. E.↗
NASA NTRS1981

Analytical calculation of thickness versus diameter requirements of silicon solar cells

It may be more cost-effective to produce larger diameter silicon Cz solar cells. However, greater thickness is anticipated to be necessary for larger diameter wafers to withstand wafering, cell processing and handling. No material standard for these dimensional requirements is practical or cost-effective for cell manufacturers. The equations relating wafer thickness and diameter were derived by using fracture mechanics analysis. An analytical model was used as a guideline to estimate thickness versus diameter requirements of silicon solar cells in terms of fracture mechanics parameters.

Chen, C. P.↗
NASA NTRS1983

High voltage v-groove solar cell

A high voltage multijunction solar cell comprises a number of discrete voltage generating regions, or unit cells, which are formed in a single semiconductor wafer and are connected together so that the voltages of the individual cells are additive. The unit cells comprise doped regions of opposite conductivity types separated by a gap. The method includes forming V-shaped grooves in the wafer and orienting the wafer so that ions of one conductivity type can be implanted in one face of the groove while the other face is shielded. A metallization layer is applied and selectively etched away to provide connections between the unit cells.

Evans, J. C., Jr.↗
NASA NTRS1984

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

Routh, D. E.↗
NASA NTRS1984

Structurally stable, thin silicon solar cells

A fabrication process for structurally stable thin solar cell wafers that produce good power output after irradiation is described. The fabrication process is as follows. A 6 mil, circular wafer is oxidized on both sides. One side is then patterned with a rectangular array of holes in the oxide that are nominally 75 mils square and separated by 2 mil spacings. Wells are then etched into the silicon with KOH to a depth of 4 mils, leaving a 2 mil, unetched thickness. Two areas on the surface are left unetched to provide pads for bonding or testing. All oxide is then removed and the rest of the processing is normal; the unetched face is used as the illuminated face. When all other processing is complete, a 2 X 2 cm cell is sawed from the starting wafer leaving a border that is approximately 10 mils wide. The effective thickness, determined by weighing an unmetallized sample, of such a cell is about 2.4 mil.

Arndt, R. A.↗
NASA NTRS1985

A mosaic infrared sensor for space astronomy, phase 3

Short wavelength (1 to 3 micron) HgCdTe mosaic detector arrays for space astronomy purposes were fabricated and studied. Honeywell will test and analyze these arrays at moderate temperatures (300-130K). Low temperature testing will be performed at the University of Hawaii. Short wavelength mosaic arrays were fabricated on three wafers and one array from each wafer was tested and analyzed. The p-type base carrier concentration on these wafers was an order of magnitude lower than typically used so far on this program (10 to the 14/cc as compared to 10 to the 15/cc). Tunneling currents are expected to decrease with this decrease in carrier concentration, resulting in improved performance at very low temperatures. The risk with such a low carrier concentration is that fixed charge in the surface passivating layer must be carefully controlled to prevent surface inversion layers.

Sood, A. K.↗
NASA NTRS1988

Fluidized-Bed Deposition Of Single-Crystal Silicon

Uniformly thin single-crystal films of silicon produced by modification of fluidized-bed-reactor technique producing polysilicon by chemical vapor deposition. Proposed for silicon wafers for flat-plate solar arrays and results in different structural and electronic properties in deposition layer desirable for specific microelectronic or solar-cell processing. In process deposition occurs on silicon wafers, kept individually at temperatures above 1,000 degree C. Heated wafers held in unheated and minimally-agitated-fluidized bed of silicon particles and in low concentration of silane.

Hsu, George C.↗
NASA NTRS1986

Stress modeling of microdiaphragm pressure sensors

A finite element program analysis was used to model the stress distribution of two monocrystalline silicon diaphragm pressure sensors. One configuration consists of an anisotropically backside etched diaphragm into a 250 micron thick, (100) oriented, silicon wafer. The diaphragm and total chip dimensions are given. The device is rigidly clamped on the back to a support substrate. Another configuration consists of a monocrystalline, (100), microdiaphragm which is formed on top of the wafer and whose area is reduced by a factor of 25 over the first configuration. The diaphragm is rigidly clamped to the silicon wafer. The stresses were calculated at a gauge pressure of 300 mm Hg and used to estimate the piezoresistive responses of resistor elements which were placed parallel and perpendicular near the diaphragm edges.

Tack, P. C.↗
NASA NTRS1987

Curved channel MCP improvement program

Blowholes and blemishes were determined to start at two stages of manufacturing. Sperical blowholes resulted from trapped gas between the high melting temperature bond glass and the MCP wafer. During thermal processing, the trapped gas expanded and displaced the softened channel glass to form a spherical inclusion. This defect was eliminated by grinding the prefritted bond wafer and channel plate wafer to a flatness which ensured intimate contact prior to fusion. Elliptical blowholes or blemishes were introduced during the fiber draw stage. Contaminants trapped between the core bar and clad tubing volatized providing large quantities of expanding gas. These pockets of gas became elongated to an ellipsoidal shape during fiber draw. Special cleanliness procedures were developed for the grinding, polishing, and acid etching of core bars. Improvements in channel curvature fabrication were implemented. The design of the shearing fixture was evaluated. A new design was developed which eliminated an off-axis moment. The shearing furnace design was evaluated. Steady state thermal conditions instead of thermal transient conditions were determined to reduce curvature nonuniformity.

Laprade, Bruce N.↗
NASA NTRS1989

High efficiency GaAs-Ge tandem solar cells grown by MOCVD

High conversion efficiency and low weight are obviously desirable for solar cells intended for space applications. One promising structure is GaAs on Ge. The advantages of using Ge wafers as substrates include the following: they offer high efficiency by forming a two-junction tandem cell; low weight combined with superior strength allows usage of thin (3 mil) wafers; and they are a good substrate for GaAs, being lattice matched, thermal expansion matched, and available as large-area wafers.

Vernon, S. M.↗
NASA NTRS1990

Development of a unique laboratory standard indium gallium arsenide detector for the 500 to 1700 micron spectral region, phase 2

In the course of this work, 5 mm diameter InGaAs pin detectors were produced which met or exceeded all of the goals of the program. The best results achieved were: shunt resistance of over 300 K ohms; rise time of less than 300 ns; contact resistance of less than 20 ohms; quantum efficiency of over 50 percent in the 0.5 to 1.7 micron range; and devices were maintained and operated at 125 C without deterioration for over 100 hours. In order to achieve the goals of this program, several major technological advances were realized, among them: successful design, construction and operation of a hydride VPE reactor capable of growing epitaxial layers on 2 inch diameter InP substrates with a capacity of over 8 wafers per day; wafer processing was upgraded to handle 2 inch wafers; a double layer Si3N4/SiO2 antireflection coating which enhances response over the 0.5 to 1.7 micron range was developed; a method for anisotropic, precisely controlled CH4/H2 plasma etching for enhancement of response at short wavelengths was developed; and electronic and optical testing methods were developed to allow full characterization of detectors with size and spectral response characteristics. On the basis of the work and results achieved in this program, it is concluded that large size, high shunt resistance, high quantum efficiency InGaAs pin detectors are not only feasible but also manufacturable on industrial scale. This device spans a significant portion of visible and near infrared spectral range and it will allow a single detector to be used for the 0.5 to 1.7 micron spectral region, rather than the presently used silicon (for 0.5 to 1.1 microns) and germanium (0.8 to 1.7 microns).

Ban, Vladimir S.↗
NASA NTRS1991

Survival of epiphytic bacteria from seed stored on the Long Duration Exposure Facility (LDEF)

This study was designed to determine the survival of microorganisms exposed to the relatively harsh conditions found in low Earth orbit (LEO). Seed of corn, sunflower, canteloupe, zucchini, bean, pea, and pumpkin cultivars were packaged in two 18 x 2.5 cm aluminum tubes; wall thickness for each tube was 1.33 mm. One seed tube was attacked to payload M0006, tray C-2; a second tube was stored at room temperature in a lab on Earth. Five lithium fluoride thermoluminescent dosimetry wafers (TLD-100 wafers) were placed in each aluminum tube. The total mean dosages for flight and ground-control TLD wafers were 210.0 and 0.9 rads, respectively. Seeds were washed for 2 hrs in a phosphate buffered saline solution. Bacteria were isolated by plating samples of the seed-washings onto dilute tryptic soy agar. Pure isolates of morphologically distinct bacteria were obtained by standard microbiological procedures. Bacteria were grouped according to colony-type and preliminary identification was completed using a fatty-acid analysis system. Bacillus spp. were the primary microoganisms that survived on seed during the experiment. Bacterial diversity and relative abundance were similar for the ground flight seed. Bacillus subtilus, B. pumilus, B. licheniformis, B. polymyxa, B. megaterium, and B. pabuli were isolated most frequently. Members of the genera Kurthia, Listeria, Micrococcus, and Arthrobacter were also isolated from flight and ground control seed. Results support the hypothesis that terrestrial microorganisms can survive long periods of time in the relatively harsh LEO environment.

Schuerger, Andrew C.↗
NASA NTRS1992

An improved heat transfer configuration for a solid-core nuclear thermal rocket engine

Interrupted flow, impingement cooling, and axial power distribution are employed to enhance the heat-transfer configuration of a solid-core nuclear thermal rocket engine. Impingement cooling is introduced to increase the local heat-transfer coefficients between the reactor material and the coolants. Increased fuel loading is used at the inlet end of the reactor to enhance heat-transfer capability where the temperature differences are the greatest. A thermal-hydraulics computer program for an unfueled NERVA reactor core is employed to analyze the proposed configuration with attention given to uniform fuel loading, number of channels through the impingement wafers, fuel-element length, mass-flow rate, and wafer gap. The impingement wafer concept (IWC) is shown to have heat-transfer characteristics that are better than those of the NERVA-derived reactor at 2500 K. The IWC concept is argued to be an effective heat-transfer configuration for solid-core nuclear thermal rocket engines.

Clark, John S.↗
NASA NTRS1993

Chemical Vapor Deposition Of Silicon Carbide

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Powell, J. Anthony↗
NASA NTRS1992

Planning for the semiconductor manufacturer of the future

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

Fargher, Hugh E.↗
NASA NTRS1992

Scheduling revisited workstations in integrated-circuit fabrication

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Kline, Paul J.↗
NASA NTRS1993

Microwave characterization of slotline on high resistivity silicon for antenna feed network

Conventional silicon wafers have low resistivity and consequently unacceptably high value of dielectric attenuation constant. Microwave circuits for phased array antenna systems fabricated on these wafers therefore have low efficiency. By choosing a silicon substrate with sufficiently high resistivity it is possible to make the dielectric attenuation constant of the interconnecting microwave transmission lines approach those of GaAs or InP. In order for this to be possible, the transmission lines must be characterized. In this presentation, the effective dielectric constant (epsilon sub eff) and attenuation constant (alpha) of a slotline on high resistivity (5000 to 10 000 ohm-cm) silicon wafer will be discussed. The epsilon sub eff and alpha are determined from the measured resonant frequencies and the corresponding insertion loss of a slotline ring resonator. The results for slotline will be compared with microstrip line and coplanar waveguide.

Simons, Rainee N.↗
NASA NTRS1992

A new fabrication technique for back-to-back varactor diodes

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

Smith, R. Peter↗