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At least 451 records · Page 25

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NASA NTRS1983

Parallel processing in a host plus multiple array processor system for radar

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

Barkan, B. Z.↗

NASA NTRS1981

Technology and future ground processing systems

Land-observing satellites with multiple thematic mappers will produce data at rates of 100 to 300 Mbps. When coupled with a high daily scene production rate, these rates will require new approaches to ground processing. Consideration is given here to future downlink rates and data volumes, and requirements peculiar to the future user community are discussed. The advanced technologies required to attain an operational system in the years 1985-1990 are considered, together with advances foreseen in communications, mass storage, bulk memories, and data processing. Using advanced devices, a centralized data processing system capable of handling the 100 Mbps data rate is described. New approaches, among them a parallel pipelined calibration front-end, real-time browse image production, a high bandwidth optical disk archive, regional image broadcast and massively parallel product production, are considered. A distributed system capable of handling the 300 Mbps data rate is then described. Designs for a hub system and a regional processing center are presented.

Wood, B. J.↗

NASA NTRS1983

Parallel architectures for computing cyclic convolutions

In the paper two parallel architectural structures are developed to compute one-dimensional cyclic convolutions. The first structure is based on the Chinese remainder theorem and Kung's pipelined array. The second structure is a direct mapping from the mathematical definition of a cyclic convolution to a computational architecture. To compute a d-point cyclic convolution the first structure needs d/2 inner product cells, while the second structure and Kung's linear array require d cells. However, to compute a cyclic convolution, the second structure requires less time than both the first structure and Kung's linear array. Another application of the second structure is to multiply a Toeplitz matrix by a vector. A table is listed to compare these two structures and Kung's linear array. Both structures are simple and regular and are therefore suitable for VLSI implementation.

Yeh, C.-S.↗

NASA NTRS1985

Real-Time Reed-Solomon Decoder

RS decoder uses dedicated hardware and data pipelining for high-speed operation. Parallel processing techniques provide equivalent of over one billion operations per second at one step in decoding. Decoder finds commercial application in data encoding/decoding, telemetry, and radio communications.

Lahmeyer, C. R.↗

NASA NTRS1985

X-Ray Determination of Weld Misalinement

Simple technique uses ordinary X-ray equipment. Weld line between hemispheres of hidden spherical pressure vessel examined for misalinement between hemispheres. Central X-ray tangent to pressure vessel at weld line. Technique not limited to spheres. Also used to check alinement between insulated sections of pipelines or chemical-reaction vessels without removing insulation or interrupting flow or process.

Nelson, C. W.↗

NASA NTRS1985

Predicting the Reliability of Solar-Cell Interconnections

The reduction of life expectancy by thermal cycling calculated during design. Connections between solar cells critical parts of solarcell arrays generating electric power. Reliability affects life expectancy of modules, panels, and arrays. Used to predict stress-cycle lifetimes of such structures as arches, walkways, cylindrical ribbing of aircraft fuselages and submarine hulls, and pipeline expansion loops. Testing costs reduced by about 90 percent.

Mon, G. R.↗

NASA NTRS1983

High-speed digital signal normalization for feature identification

A design approach for high speed normalization of digital signals was developed. A reciprocal look up table technique is employed, where a digital value is mapped to its reciprocal via a high speed memory. This reciprocal is then multiplied with an input signal to obtain the normalized result. Normalization improves considerably the accuracy of certain feature identification algorithms. By using the concept of pipelining the multispectral sensor data processing rate is limited only by the speed of the multiplier. The breadboard system was found to operate at an execution rate of five million normalizations per second. This design features high precision, a reduced hardware complexity, high flexibility, and expandability which are very important considerations for spaceborne applications. It also accomplishes a high speed normalization rate essential for real time data processing.

Ortiz, J. A.↗

NASA NTRS1983

Catalog of selected heavy duty transport energy management models

A catalog of energy management models for heavy duty transport systems powered by diesel engines is presented. The catalog results from a literature survey, supplemented by telephone interviews and mailed questionnaires to discover the major computer models currently used in the transportation industry in the following categories: heavy duty transport systems, which consist of highway (vehicle simulation), marine (ship simulation), rail (locomotive simulation), and pipeline (pumping station simulation); and heavy duty diesel engines, which involve models that match the intake/exhaust system to the engine, fuel efficiency, emissions, combustion chamber shape, fuel injection system, heat transfer, intake/exhaust system, operating performance, and waste heat utilization devices, i.e., turbocharger, bottoming cycle.

Colello, R. G.↗

NASA NTRS1984

Optical systolic solutions of linear algebraic equations

The philosophy and data encoding possible in systolic array optical processor (SAOP) were reviewed. The multitude of linear algebraic operations achievable on this architecture is examined. These operations include such linear algebraic algorithms as: matrix-decomposition, direct and indirect solutions, implicit and explicit methods for partial differential equations, eigenvalue and eigenvector calculations, and singular value decomposition. This architecture can be utilized to realize general techniques for solving matrix linear and nonlinear algebraic equations, least mean square error solutions, FIR filters, and nested-loop algorithms for control engineering applications. The data flow and pipelining of operations, design of parallel algorithms and flexible architectures, application of these architectures to computationally intensive physical problems, error source modeling of optical processors, and matching of the computational needs of practical engineering problems to the capabilities of optical processors are emphasized.

Neuman, C. P.↗

NASA NTRS1983

A parallel architecture for digital filtering using Fermat number transforms

In this correspondence, a parallel architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT). In particular, a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. The overlap-save method is generalized for the FNT to realize a digital filter of arbitrary length. The generalized overlap-save method alleviates the usual dynamic range limitation of FNT's of long transform lengths. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNT's of 128 points. Its architecture is regular, simple, and flexible, and therefore naturally suitable for VLSI implementation.

Truong, T. K.↗

NASA NTRS1983

Integrated optical circuits for numerical computation

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

Verber, C. M.↗

NASA NTRS1983

Large array VLSI filter

A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.

Nathan, R.↗

NASA NTRS1984

Optical Kalman filtering for missile guidance

Optical systolic array processors constitute a powerful and general-purpose set of optical architectures with high computational rates. In this paper, Kalman filtering, a novel application for these architectures, is investigated. All required operations are detailed; their realization by optical and special-purpose analog electronics are specified; and the processing time of the system is quantified. The specific Kalman filter application chosen is for an air-to-air missile guidance controller. The architecture realized in this paper meets the design goal of a fully adaptive Kalman filter which processes a measurement every 1 msec. The vital issue of flow and pipelining of data and operations in a systolic array processor is addressed. The approach is sufficiently general and can be realized on an optical or digital systolic array processor.

Casasent, D.↗

NASA NTRS1984

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Casasent, D.↗

NASA NTRS1984

Offshore oil in the Alaskan Arctic

Oil and gas deposits in the Alaskan Arctic are estimated to contain up to 40 percent of the remaining undiscovered crude oil and oil-equivalent natural gas within U.S. jurisdiction. Most (65 to 70 percent) of these estimated reserves are believed to occuur offshore beneath the shallow, ice-covered seas of the Alaskan continental shelf. Offshore recovery operations for such areas are far from routine, with the primary problems associated with the presence of ice. Some problems that must be resolved if efficient, cost-effective, environmentally safe, year-round offshore production is to be achieved include the accurate estimation of ice forces on offshore structures, the proper placement of pipelines beneath ice-produced gouges in the sea floor, and the cleanup of oil spills in pack ice areas.

Weeks, W. F.↗

NASA NTRS1985

Automated Coal-Mining System

Proposed system offers safety and large return on investment. System, operating by year 2000, employs machines and processes based on proven principles. According to concept, line of parallel machines, connected in groups of four to service modules, attacks face of coal seam. High-pressure water jets and central auger on each machine break face. Jaws scoop up coal chunks, and auger grinds them and forces fragments into slurry-transport system. Slurry pumped through pipeline to point of use. Concept for highly automated coal-mining system increases productivity, makes mining safer, and protects health of mine workers.

Gangal, M. D.↗

NASA NTRS1986

Systolic VLSI Reed-Solomon Decoder

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Shao, H. M.↗

NASA NTRS1986

Fast VLSI Viterbi Decoder

Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.

Wang, C. C.↗