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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Nanosecond Laser Drying in Wafer Foundries for Significant Energy Efficiency Improvement

Surface drying is a critical process in microelectronics wafer fabrication. In order to reduce and eliminate watermarks, many surface drying processes have been studied and used. Most of the wafer foundries currently use drying processes based on Isopropyl Alcohol (IPA), which causes serious safety (fire), health, environmental, and energy efficiency issues. The long-term goal of this project is to develop a fast, effective, chemical-free, and extremely energy efficient wafer drying technology that employs nanosecond laser-induced sub-surface evaporation and explosion. The objectives of this project are to 1) experimentally develop and verify the laser surface drying method, explore and identify how and to what extent various physical parameters influence the drying efficiency and effectiveness; and 2) understand and optimize the underlying thermodynamics in the proposed laser surface drying, including micro/nanoscale sub-surface superheating, evaporation, explosion, and photo/thermochemical bond breaking via atomistic modeling and experimental characterization. Toward these objectives, five tasks have been accomplished successfully, including 1) develop in-lab laser surface drying setup and study the effect of varied laser parameters, 2) use multiscale hybrid-modeling to study and understand the physics of water behavior during drying toward process optimization, 3) investigate the effect of drying conditions on the drying effectiveness, 4) develop a large-scale laser drying scanning system with automatic scanning, and 5) conduct large-scale simulation to study the effect of dopant level and develop strategies for system development toward industry deployment.

42 ENGINEERING↗
NASA NTRS1998

NASA Center for Integrated Space Microsystems

Develop and maintain a world class, leading edge capability in Advanced Avionic Systems and Advanced Microelectronics Technologies for future highly integrated, miniaturized, autonomous spacecraft systems for deep-space and Earth orbiting missions.

CISM Avionics Microelectronics Miniaturization Aut↗
NASA NTRS1998

Space Radiation Environment

Coupled with the increasing concern over trapped radiation effects on microelectronics, the availability of new data, long term changes in the Earth's magentic field, and observed variations in the trapped radiation fluxes have generated the need for better, more comprehensive tools for modeling and predicting the Earth's trapped radiation environment and its effects on space systems.

Earth's magentic field trapped radiation environme↗
NASA NTRS1995

Magnetic Device Design and Evaluation Capabilities at JPL

This viewgraph presentation describes the magnetic device design and evaluation capabilities at the Center for Space Microelectronics Technology at the Jet Propulsion Laboratory. The capabilities start with supercomputers for design and simulation. Circuits can be examined via electrical flow and microscopic examination. These capabilities are useful for developing new devices, particularly for space applications.

microelectronics chip testing magnetic devices↗
NASA NTRS1994

Fluorine Implantation and Residual Stresses in Polysilicon Films

As microelectronic device dimensions are reduced below one micron, the hot carrier effect is a major barrier to continued scaling and VLSI reliability. Several reports have shown that fluorine diffusion into the device gate greatly enhances the resistance to hot carriers. There has been some disagreement as to the mechanism of influence; however, several reports have suggested that the polysilicon is physically modified by the fluorine implant and that the beneficial effects are at least in part due to stress relaxation in the polysilicon.

polysilicon fluorine microelectronic devices hot c↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS2018

The International Space Station Space Radiation Environment: Avionics Systems Performance in Low-Earth Orbit Single Event Effects (SEE) Environments

Single event effects (SEE) are those errors, anomalies, or failures in microelectronic devices caused by the passage of a single energetic charged particle through the device. Spacecraft SEE environments consist primarily of energetic charged particles; both primary particles originating in the natural environment and secondary particles (including secondary neutrons) produced by nuclear reactions of primary particles with spacecraft materials. The energetic charged particle components (electrons, protons, and atomic nuclei) of the spacecraft SEE environment include galactic cosmic rays (GCR), and planetary radiation belt charged particles, as well as solar energetic particle event (SPE) charged particles. The International Space Station (ISS) orbital altitude and inclination (~350 km to ~420 km at 51.6o inclination) results in a spacecraft SEE environment that varies dramatically with the location in Earth?s geomagnetic field. Geomagnetic GCR shielding diminishes with distance from the geomagnetic equator. Near + 51.6o latitude the ISS GCR environment has a high degree of similarity to the interplanetary GCR environment in cis-Lunar space.SEE environments supporting ISS avionics systems design, development, test, and verification are documented in SSP-30512, Space Station Ionizing Radiation Design Environment. Comparisons of overall ISS avionics systems in-flight performance with pre-flight verification report predictions have been previously reported and meet or exceed expectations in all cases.In this paper we report the results of more detailed investigations of the effects of geographic location, altitude, solar cycle, and shielding mass effects on the in-flight SEE performance of the ISS command and data handling system during the past 17 years. In addition, we report on the preflight testing and in-flight performance of the commercial-off-the-shelf lap top computers used on ISS. Finally, we present an assessment of ISS as an avionics SEE test and flight demonstration platform for exploration hardware destined for the cis-lunar or other inner solar system environments.

International Space Station↗
DOE OSTI2020

Freestanding Photoresist Film: A Versatile Template for Three-Dimensional Micro- and Nanofabrication

Ultrathin freestanding films with well-defined micro/nanostructures and robust mechanical properties are applied in many engineering applications including microelectronics, optics, filtration and separation, biomedical engineering, and nanotechnology. Although considerable efforts have been made toward the fabrication of freestanding thin films, it is still a significant challenge to develop a simple and reliable process for producing freestanding films with ultrathin thickness, well-regulated micro/nanopatterns, robust mechanical properties, macroscopic coverage area, and multi-layered composite structures. In this work, a significant advancement is reported in this regard. This study shows a new sacrificial-layer-free (SLF) lifting-off process, integrated with conventional micro- and nanolithography, enabling the release of micro- and nanopatterned photoresist (PR) films from the supporting substrate with unprecedented pattern coverage and structure characteristics. The freestanding PR film is resilient, can withstand significant bending and deformation, and is sufficiently flexible to be transferred onto substrates with 3D topography as a conformal soft stencil for further technological processing and applications. Moreover, the SLF lifting-off process provides a simple approach to prepare single-layered and multi-layered freestanding composite films. The results suggest that the novel SLF lifting-off process can significantly extend the capability of 3D micro-/nanofabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Dominant Energy Carrier Transitions and Thermal Anisotropy in Epitaxial Iridium Thin Films

High aspect ratio metal nanostructures are commonly found in a broad range of applications such as electronic compute structures and sensing. The self-heating and elevated temperatures in these structures, however, pose a significant bottleneck to both the reliability and clock frequencies of modern electronic devices. Any notable progress in energy efficiency and speed requires fundamental and tunable thermal transport mechanisms in nanostructured metals. Here, in this work, time-domain thermoreflectance is used to expose cross-plane quasi-ballistic transport in epitaxially grown metallic Ir(001) interposed between Al and MgO(001). Thermal conductivities ranges from roughly 65 (96 in-plane) to 119 (122 in-plane) W m -1 K -1 for 25.5–133.0 nm films, respectively. Further, low defects afforded by epitaxial growth are suspected to allow the observation of electron–phonon coupling effects in sub-20 nm metals with traditionally electron-mediated thermal transport. Via combined electro-thermal measurements and phenomenological modeling, the transition is revealed between three modes of cross-plane heat conduction across different thicknesses and an interplay among them: electron dominant, phonon dominant, and electron–phonon energy conversion dominant. The results substantiate unexplored modes of heat transport in nanostructured metals, the insights of which can be used to develop electro-thermal solutions for a host of modern microelectronic devices and sensing structures.

36 MATERIALS SCIENCE↗