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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

System Assessment of a High Power 3-U CubeSat

The Advanced eLectrical Bus (ALBus) CubeSat project is a technology demonstration mission of a 3-UCubeSat with an advanced, digitally controlled electrical power system capability and novel use of Shape Memory Alloy (SMA) technology for reliable deployable solar array mechanisms. The objective of the project is to, through an on orbit demonstration, advance the state of power management and distribution (PMAD) capabilities to enable future missions requiring higher power, flexible and reliable power systems. The goals of the mission include demonstration of: 100 Watt distribution to a target electrical load, efficient battery charging in the orbital environment, flexible power system distribution interfaces, adaptation of power system control on orbit, and reliable deployment of solar arrays and antennas utilizing re-settable SMA mechanisms. The power distribution function of the ALBus PMAD system is unique in the total power to target load capability of 100 W, the flexibility to support centralized or point-to-load regulation and ability to respond to fast transient power requirements. Power will be distributed from batteries at 14.8 V, 6.5 A to provide 100 W of power directly to a load. The deployable solar arrays utilize NASA Glenn Research Center superelastic and activated Nitinol(Nickel-Titanium alloy) Shape Memory Alloy (SMA) technology for hinges and a retention and release mechanism. The deployable solar array hinge design features utilization of the SMA material properties for dual purpose. The hinge uses the shape memory properties of the SMA to provide the spring force to deploy the arrays. The electrical conductivity properties of the SMA also enables the design to provide clean conduits for power transfer from the deployable arrays to the power management system. This eliminates the need for electrical harnesses between the arrays and the PMAD system in the ALBus system design. The uniqueness of the SMA retention and release mechanism design is the ability to reset the mechanism, allowing functional tests of the mechanisms prior to flight with no degradation of performance. The project is currently in preparation at the NASA Glenn Research Center for a launch in late calendar year of 2017. The 100 Watt power distribution and dual purpose, re-settable SMA mechanisms introduced several system level challenges due to the physical constraints in volume, mass and surface area of 3-U CubeSats. Several trade studies and design cycles have been completed to develop a system which supports the project objectives. This paper is a report on the results of the system level trade studies and assessments. The results include assessment of options for thermal control of 100 Watts of power dissipation, data from system analyses and engineering development tests, limitations of the 3-U system and extensibility to larger scale CubeSat missions.

CubeSat↗
NASA NTRS1981

System performance analyzer

The System Performance Analyzer (SPA) designed to provide accurate real time information about the operation of complex systems and developed for use on the Airborne Data Analysis/Monitor System (ADAMS), a ROLM 1666 based system is described. The system uses an external processor to operate an intelligent, simulated control panel. Also provided are functions to trace operations, determine frequency of use of memory areas, and time or count user tasks in a multitask environment. This augments the information available from the standard debugger and control panel, and reduces the time and effort needed by ROLM 1666 users in optimizing their system, as well as providing documentation of the effect of any changes. The operation and state of the system are evaluated.

Helbig, H. R.↗
NASA NTRS1994

Integrated, nonvolatile, high-speed analog random access memory

This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

Katti, Romney R.↗
DOE OSTI2025

Machine learning modeling and model predictive control of a closed-circuit reverse osmosis system

Closed-circuit reverse osmosis (CCRO) offers a flexible and energy-efficient alternative to conventional reverse osmosis by operating in a semi-batch mode that recycles brine, enabling higher recovery rates and reduced specific energy consumption (SEC). However, developing accurate, system-level dynamic models for CCRO remains challenging due to its nonlinear, multi-phase operation and sensitivity to variable feed water conditions. Traditional modeling approaches, such as NARMAX (nonlinear autoregressive moving average with exogenous inputs), often struggle to generalize across varying inlet feed concentrations, necessitating frequent parameter re-estimation and limiting their utility for real-time control applications. To address these limitations, we developed a long short-term memory (LSTM) neural network model trained on an extensive experimental data set from a CCRO pilot plant. The model accepts three inputs, feed flow rate, recirculation flow rate, and initial feed conductivity, and predicts three key outputs: reject conductivity, feed pump power draw, and recirculation pump power draw. We validated the LSTM model against experimental data, demonstrating its ability to distinguish between different feed conductivities and adapt to variable flow rates. Subsequently, we incorporated the LSTM model within a nonlinear model predictive control (MPC) scheme and conducted closed-loop simulations to optimize the integrated SEC (iSEC). In conclusion, the results project up to a 6% reduction in iSEC by using MPC to optimize performance over the entire experiment duration, without requiring any random excitation for data collection or parameter re-estimation.

Desalination↗
DOE OSTI2020

System and method for controlling an energy beam of an additive manufacturing system

An additive manufacturing system includes an energy beam generator that generates an energy beam to melt and fuse raw materials for a part and a computing device that controls operation of the energy beam generator. The computing device includes a memory element that stores or access a three-dimensional model of the part, and a processing element that receives at least a portion of the three-dimensional model and controls a parameter of the energy beam generator according to a gradient function so as to apply a variable amount of heat to the raw material that forms an overhang on the part.

42 ENGINEERING↗
NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗
NASA NTRS1984

Method and apparatus for pulse width modulation control of an AC induction motor

An inverter is connected between a source of DC power and a three-phase AC induction motor, and a micro-processor-based circuit controls the inverter using pulse width modulation techniques. In the disclosed method of pulse width modulation, both edges of each pulse of a carrier pulse train are equally modulated by a time proportional to sin .THETA., where .THETA. is the angular displacement of the pulse center at the motor stator frequency from a fixed reference point on the carrier waveform. The carrier waveform frequency is a multiple of the motor stator frequency. The modulated pulse train is then applied to each of the motor phase inputs with respective phase shifts of 120.degree. at the stator frequency. Switching control commands of electronic switches in the inverter are stored in a random access memory (RAM) and the locations of the RAM are successively read out in a cyclic manner, each bit of a given RAM location controlling a respective phase input of the motor. The DC power source preferably comprises rechargeable batteries and all but one of the electronic switches in the inverter can be disabled, the remaining electronic switch being part of a flyback DC-DC converter circuit for recharging the battery.

Geppert, Steven↗
NASA NTRS1985

Pulse width modulation inverter with battery charger

An inverter is connected between a source of DC power and a three-phase AC induction motor, and a microprocessor-based circuit controls the inverter using pulse width modulation techniques. In the disclosed method of pulse width modulation, both edges of each pulse of a carrier pulse train are equally modulated by a time proportional to sin .theta., where .theta. is the angular displacement of the pulse center at the motor stator frequency from a fixed reference point on the carrier waveform. The carrier waveform frequency is a multiple of the motor stator frequency. The modulated pulse train is then applied to each of the motor phase inputs with respective phase shifts of 120.degree. at the stator frequency. Switching control commands for electronic switches in the inverter are stored in a random access memory (RAM) and the locations of the RAM are successively read out in a cyclic manner, each bit of a given RAM location controlling a respective phase input of the motor. The DC power source preferably comprises rechargeable batteries and all but one of the electronic switches in the inverter can be disabled, the remaining electronic switch being part of a flyback DC-DC converter circuit for recharging the battery.

Slicker, James M.↗
DOE OSTI2022

Sensitivity Study of Mini-Batch Size on a Long Short-Term Memory Network for In-situ Sensing of Core-to-shell Ratio of Microencapsulated Phase Change Materials

Microencapsulated phase change materials are being studied for applications for thermal energy storage in concentrated solar fields. During fabrication, the thickness of the encapsulation cannot be readily measured for real-time control. Therefore, a machine learning network, specifically a Long Short-Term Memory network, is being developed to estimate the ratio of the shell radius to core radius based on a one second temperature history. The mini-batch size determines how often the algorithm weights are updated during network training, and shuffle indicates whether the training data is shuffled during training. A general factorial design is used to analyze the effects of varying mini-batch size and shuffle, along with the core-to-shell ratio, on the RMSE of the response from the Long Short-Term Memory network. It was found that the network performed better for smaller core to shell ratios (less than 0.6) and had the lowest RMSE when the minibatch size was 128. The minimum RMSE found was 0.00501.

Shannon, Rebecca↗
NASA NTRS2006

Challenges and Progress in the Development of High-Temperature Shape Memory Alloys Based on NiTiX Compositions for High-Force Actuator Applications

Interest in high-temperature shape memory alloys (HTSMA) has been growing in the aerospace, automotive, process control, and energy industries. However, actual materials development has seriously lagged component design, with current commercial NiTi alloys severely limited in their temperature capability. Additions of Pd, Pt, Au, Hf, and Zr at levels greater than 10 at.% have been shown to increase the transformation temperature of NiTi alloys, but with few exceptions, the shape memory behavior (strain recovery) of these NiTiX systems has been determined only under stress free conditions. Given the limited amount of basic mechanical test data and general lack of information regarding the work attributes of these materials, a program to investigate the mechanical behavior of potential HTSMAs, with transformation temperatures between 100 and 500 C, was initiated. This paper summarizes the results of studies, focusing on both the practical temperature limitations for ternary TiNiPd and TiNiPt systems based on the work output of these alloys and the ability of these alloys to undergo repeated thermal cycling under load without significant permanent deformation or "walking". These issues are ultimately controlled by the detwinning stress of the martensite and resistance to dislocation slip of the individual martensite and austenite phases. Finally, general rules that govern the development of useful, high work output, next-generation HTSMA materials, based on the lessons learned in this work, will be provided

Padula, Santo, II↗
DOE OSTI2022

Manipulating the insulator–metal transition through tip-induced hydrogenation

Manipulating the insulator–metal transition in strongly correlated materials has attracted a broad range of research activity due to its promising applications in, for example, memories, electrochromic windows and optical modulators. Electric-field-controlled hydrogenation using ionic liquids and solid electrolytes is a useful strategy to obtain the insulator–metal transition with corresponding electron filling, but faces technical challenges for miniaturization due to the complicated device architecture. Here, in this work, we demonstrate reversible electric-field control of nanoscale hydrogenation into VO 2 with a tunable insulator–metal transition using a scanning probe. The Pt-coated probe serves as an efficient catalyst to split hydrogen molecules, while the positive-biased voltage accelerates hydrogen ions between the tip and sample surface to facilitate their incorporation, leading to non-volatile transformation from insulating VO 2 into conducting H x VO 2 . Remarkably, a negative-biased voltage triggers dehydrogenation to restore the insulating VO 2 . This work demonstrates a local and reversible electric-field-controlled insulator–metal transition through hydrogen evolution and presents a versatile pathway to exploit multiple functional devices at the nanoscale.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Polariton-Based Quantum Memristors

Information processing and storage by the same physical system is emerging as a promising alternative to traditional computing platforms. In turn, this requires the realization of elementary units the memory content of which can be easily tuned and controlled. In this work, we introduce a polariton-based quantum memristor where the memristive nature arises from the intercavity polariton exchange and is controlled by a time-varying atom-cavity detuning. A dynamical hysteresis is characterized by the fluctuations in the instantaneous polariton number, where the history information is encoded into a dynamical phase. Using a Lindblad master-equation approach, we find that features of the quantum memristor dynamics, such as the area and circulation of the hysteresis loop, showcase a kind of “plasticity” controlled by quantum state initialization. This makes this quantum memristor very versatile for a wide range of applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Deep learning-assisted modeling for χ (2) nonlinear optics

Modeling second-order (χ(2)) nonlinear optical processes remains computationally expensive due to the need to resolve fast field oscillations and simulate wave propagation using methods such as the split-step Fourier method (SSFM). This can become a bottleneck in real-time applications, such as high-repetition-rate laser systems requiring rapid feedback and control. We present a long short-term memory-based surrogate model trained on SSFM simulations generated from a start-to-end model of the photocathode drive laser at SLAC National Accelerator Laboratory’s Linac Coherent Light Source II. The model achieves over 250× speedup while maintaining high fidelity, enabling future real-time optimization and laying the foundation for data-integrated modeling frameworks and digital twins of laser systems.

Accelerator Physics (physics.acc-ph)↗
NASA NTRS1976

HEP - A semaphore-synchronized multiprocessor with central control

The paper describes the design concept of the Heterogeneous Element Processor (HEP), a system tailored to the special needs of scientific simulation. In order to achieve high-speed computation required by simulation, HEP features a hierarchy of processes executing in parallel on a number of processors, with synchronization being largely accomplished by hardware. A full-empty-reserve scheme of synchronization is realized by zero-one-valued hardware semaphores. A typical system has, besides the control computer and the scheduler, an algebraic module, a memory module, a first-in first-out (FIFO) module, an integrator module, and an I/O module. The architecture of the scheduler and the algebraic module is examined in detail.

Gilliland, M. C.↗
NASA NTRS1981

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Lindgren, R. W.↗
NASA NTRS1980

Asynchronous interactive control systems

A class of interactive control systems is derived by generalizing interactive manipulator control systems. The general structural properties of such systems are discussed and an appropriate general software implementation is proposed. This is based on the fact that tasks of interactive control systems can be represented as a network of a finite set of actions which have specific operational characteristics and specific resource requirements, and which are of limited duration. This has enabled the decomposition of the overall control algorithm into a set of subalgorithms, called subcontrollers, which can operate simultaneously and asynchronously. Coordinate transformations of sensor feedback data and actuator set-points have enabled the further simplification of the subcontrollers and have reduced their conflicting resource requirements. The modules of the decomposed control system are implemented as parallel processes with disjoint memory space communicating only by I/O. The synchronization mechanisms for dynamic resource allocation among subcontrollers and other synchronization mechanisms are also discussed in this paper. Such a software organization is suitable for the general form of multiprocessing using computer networks with distributed storage.

Vuskovic, M. I.↗
NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗
NASA NTRS1982

Beyond the supercomputer

A NASA-directed development of massively parallel processor (MPP) computers is outlined, noting intended applications for data processing for near term earth resource and environment mapping, radar, and television transmissions. The MPP is designed to perform 100 billion operations/sec to obtain satisfactory image processing, while separate processing units correct distortions, register images, calculate correlation functions, and classify multispectral characteristics. Arrays of 1s and 0s will be manipulated in analog-to-digital conversions generating separate planes corresponding to powers of binaries. Data wires are replaced by fiber-optic tubes or thousands of wires, and single logic gates are replaced by thousands of logic gates and every memory element by thousands of memory elements. Features of the interconnections and the images control processor units are detailed, along with implementation of sliders for program flexibility.

Schaefer, D. H.↗