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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
DOE OSTI2016

Memory cell operation based on small Josephson junctions arrays

Here in this article we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

The neutrino gravitational memory from a core collapse supernova: phenomenology and physics potential

General Relativity predicts that the passage of matter or radiation from an asymmetrically-emitting source should cause a permanent change in the local space-time metric. This phenomenon, called the gravitational memory effect, has never been observed, however supernova neutrinos have long been considered a promising avenue for its detection in the future. With the advent of deci-Hertz gravitational wave interferometers, observing the supernova neutrino memory will be possible, with important implications for multimessenger astronomy and for tests of gravity. In this work, we develop a phenomenological (analytical) toy model for the supernova neutrino memory effect, which is overall consistent with the results of numerical simulations. This description is then generalized to several case studies of interest. We find that, for a galactic supernova, the dimensionless strain, h(t), is of order ~ 10 -22 - 10 -21 , and develops over a typical time scale that varies between ~ 0.1 - 10 s, depending on the time-evolution of the anisotropy of the neutrino emission. The characteristic strain, h c (f), has a maximum at a frequency f max ~ Script $\mathcal{O}$(10 -1 ) - Script $\mathcal{O}$(1) Hz. The detailed features of the time- and frequency-structure of the memory strain will inform us of the matter dynamics near the collapsed core, and allow to distinguish between different stellar collapse scenarios. Next generation gravitational wave detectors like DECIGO and BBO will be sensitive to the neutrino memory effect for supernovae at typical galactic distances and beyond; with Ultimate DECIGO exceeding a detectability distance of 10 Mpc

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Plasma phosphorylated tau217 strongly associates with memory deficits in the Alzheimer’s disease spectrum

Abstract Plasma phosphorylated tau (p-tau) biomarkers open unprecedented opportunities for identifying carriers of Alzheimer’s disease pathophysiology in early disease stages using minimally invasive techniques. Plasma p-tau biomarkers are believed to reflect tau phosphorylation and secretion. However, it remains unclear to what extent the magnitude of plasma p-tau abnormalities reflects neuronal network disturbance in the form of cognitive impairment. To address this question, we included 103 cognitively unimpaired elderly and 40 cognitively impaired, amyloid-β-positive individuals from the TRIAD cohort, in addition to 336 cognitively unimpaired and 216 cognitively impaired, amyloid-β-positive older adults from the BioFINDER-2 cohort. Participants had tau PET scans, amyloid PET scans or amyloid CSF, p-tau217, p-tau181 and p-tau231 blood measures, structural T1-MRI and cognitive assessments. In this cross-sectional study, we used regression models and correlation analyses to assess the relationship between plasma biomarkers and cognitive scores. Furthermore, we applied receiver operating characteristic curves to assess cognitive impairment across plasma biomarkers. Finally, we categorized participants into amyloid (A), p-tau (T1) and tau PET (T2) positive (+) or negative (−) profiles and ran non-parametric comparisons to assess differences across cognitive domains. We found that plasma p-tau217 was more associated with cognitive performance than p-tau181 and p-tau231 and that this relationship was particularly strong for memory scores (TRIAD: βp-tau217 = −0.53, βp-tau181 = −0.35 and βp-tau231 = −0.24; BioFINDER-2: βp-tau217 = −0.52, βp-tau181 = −0.24 and βp-tau231 = −0.29). Associations in amyloid-β-positive participants resembled these results, but other cognitive scores also showed strong associations in cognitively impaired individuals. Moreover, plasma p-tau217 outperformed plasma p-tau181 and plasma p-tau231 in identifying memory impairment (area under the curve values for TRIAD: p-tau217 = 0.86, p-tau181 = 0.77 and p-tau231 = 0.75; and for BioFINDER-2: p-tau217 = 0.86, p-tau181 = 0.76 and p-tau231 = 0.81) and in identifying executive function impairment only in the BioFINDER-2 cohort (p-tau217 = 0.82, p-tau181 = 0.76 and p-tau231 = 0.76). Lastly, we showed that subtle memory deficits were present in A+T1+T2− participants for plasma p-tau217 (P = 0.007) and plasma p-tau181 (P = 0.01) in the TRIAD cohort and for all biomarkers across cognitive domains in A+T1+T2− and A+T1+T2− individuals (P < 0.001 in all) in the BioFINDER-2 cohort. The A+T1+T2− individuals showed cognitive deficits in both cohorts (P < 0.001 in all). Together, our results suggest that plasma p-tau217 stands out as a biomarker capable of identifying memory deficits attributable to Alzheimer’s disease and that memory impairment certainly occurs in amyloid-β- and plasma p-tau-positive individuals who have no significant amounts of tau in the neocortex.

Neurosciences & Neurology↗
DOE OSTI2017

Memory in de Sitter space and Bondi-Metzner-Sachs-like supertranslations

It is well known that the memory effect in flat spacetime is parametrized by the Bondi-Metzner-Sachs (BMS) supertranslation. We investigate the relation between the memory effect and diffeomorphism in de Sitter spacetime. We find that gravitational memory is parametrized by a BMS-like supertranslation in the static patch of de Sitter spacetime. We also show a diffeomorphism that corresponds to gravitational memory in the Poincare/cosmological patch. Our method does not need to assume the separation between the source and the detector to be small compared with the Hubble radius, and can potentially be applicable to other Friedmann-Lemaitre-Robertson-Walker universes, as well as “ordinary memory” mediated by massive messenger particles.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2015

Exploring Memory Hierarchy to Improve Scientific Data Read Performance, In: 2015 IEEE International Conference on Cluster Computing

Improving read performance is one of the major challenges with speeding up scientific data analytic applications. Utilizing the memory hierarchy is one major line of researches to address the read performance bottleneck. Related methods usually combine solide-state-drives(SSDs) with dynamic random-access memory(DRAM) and/or parallel file system(PFS) to mitigate the speed and space gap between DRAM and PFS. However, these methods are unable to handle key performance issues plaguing SSDs, namely read contention that may cause up to 50% performance reduction. In this paper, we propose a framework that exploits the memory hierarchy resource to address the read contention issues involved with SSDs. The framework employs a general purpose online read algorithm that able to detect and utilize memory hierarchy resource to relieve the problem. To maintain a near optimal operating environment for SSDs, the framework is able to orchastrate data chunks across different memory layers to facilitate the read algorithm. Compared to existing tools, our framework achieves up to 50% read performance improvement when tested on datasets from real-world scientific simulations.

Computer Science↗
DOE OSTI2022

MemGaze: Rapid and Effective Load-Level Memory Trace Analysis

A major challenge of memory analysis tools is combining high-resolution analysis and low overhead measurement. Currently, hardware/software-based analysis of load-level sequences incurs time slowdowns of O(100×). We present MemGaze, a tool for low-overhead, high-resolution memory analysis. MemGaze uses Intel’s Processor Tracing (PT) instruction ptwrite to collect sampled and compressed memory address traces for load-level, sequence-aware analysis of data reuse. We describe multi-resolution analysis for locations vs. operations, accesses vs. spatio-temporal reuse, and reuse (distance, rate, volume) vs. access patterns. Both trace size and resolution are controllable. We use MemGaze to elucidate the memory effects of different data structures and algorithms. For sampled traces that are ˜1% of a full one, analysis metrics have 1-25% MAPE for histograms of varying dynamic sequence lengths. With current suboptimal kernel support (PT runs continuously), MemGaze’s time overhead is typically 10–95%; 7× at worst. However, when PT runs only during samples, overhead is 10–35% on memory intensive regions and correlates with executed ptwrites.

Kilic, Ozgur O.↗
DOE OSTI2023

IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing

This paper proposes an efficient data memory management approach for the Intelligent RuntIme System (IRIS) heterogeneous computing framework along with new data transfer policies. IRIS provides a task-based programming model for extreme heterogeneous computing (e.g., CPU, GPU, DSP, FPGA) with support for today's most important programming languages (e.g., OpenMP, OpenCL, CUDA, HIP, OpenACC). However, the IRIS framework either forces the programmer to introduce data transfer commands for each task or relies on suboptimal memory management for automatic and transparent data transfers. The work described here extends IRIS with novel heterogeneous memory handling and introduces novel data transfer policies by employing the Distributed data MEMory handler (DMEM) for efficient and optimal movement of data among the various computing resources. The proposed approach achieves performance gains of up to 7× for tiled LU factorization and tiled DGEMM (i.e., matrix multiplication) benchmarks. Moreover, this approach also reduces data transfers by up to 71% when compared to previous IRIS heterogeneous memory management handlers. This work compares the performance results of the IRIS framework's novel DMEM with the StarPU runtime and MAGMA math library for GPUs. Experiments show a performance gain of up to 1.95× over StarPU and 2.1× over MAGMA.

Miniskar, Narasinga Rao↗
DOE OSTI2022

Image Gradient Decomposition for Parallel and Memory-Efficient Ptychographic Reconstruction

Ptychography is a popular microscopic imaging modality for many scientific discoveries and sets the record for highest image resolution. Unfortunately, the high image resolution for ptychographic reconstruction requires significant amount of memory and computations, forcing many applications to compromise their image resolution in exchange for a smaller memory footprint and a shorter reconstruction time. In this paper, we propose a novel image gradient decomposition method that significantly reduces the memory footprint for ptychographic reconstruction by tessellating image gradients and diffraction measurements into tiles. In addition, we propose a parallel image gradient decomposition method that enables asynchronous point-to-point communications and parallel pipelining with minimal overhead on a large number of GPUs. Our experiments on a Titanate material dataset (PbTiO3) with 16632 probe locations show that our Gradient Decomposition algorithm reduces memory footprint by 51 times. In addition, it achieves time-to-solution within 2.2 minutes by scaling to 4158 GPUs with a super-linear strong scaling efficiency at 364% compared to runtimes at 6 GPUs. This performance is 2.7 times more memory efficient, 9 times more scalable and 86 times faster than the state-of-the-art algorithm.

Wang, Xiao↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
DOE OSTI2025

Error-Free and Current-Driven Synthetic Antiferromagnetic Domain Wall Memory Enabled by Channel Meandering

We propose a new type of energy-efficient multi-bit magnetic memory based on current-driven, field-free, controlled domain wall motion. A meandering domain wall channel with precisely interspersed pinning regions provides the multi-bit capability of a magnetic tunnel junction memory. The magnetic free layer of the memory device has perpendicular magnetic anisotropy (PMA) and interfacial Dzyaloshinskii-Moriya interaction (DMI) so that spin-orbit torques (SOTs) induce efficient domain wall motion. Using micromagnetic simulations, we find two different cell designs: two-way switching and four-way switching. The memory cell design choices and the physics of pinning mechanisms are discussed in detail. Furthermore, we show that switching reliability and speed may be significantly improved by replacing the ferromagnetic free layer with a synthetic antiferromagnetic (SAF) layer. Switching behavior and material choices will be discussed for the two memory implementations.

magnetic domain wall↗
DOE OSTI2025

Generalizing multiple memories from a single drive: The hysteron latch

Far-from-equilibrium systems can form memories of previous deformations or driving. In systems from sheared glassy materials to buckling beams to crumpled sheets, this behavior is dominated by return-point memory, in which revisiting a past extremum of driving restores the system to a previous state. Cyclic driving with both positive and negative strains forms multiple nested memories, as in a single-dial combination lock, while asymmetric driving (only positive strain) cannot. We study this case in a general model of hysteresis that considers discrete elements called hysterons. We show how two hysterons with a frustrated interaction can violate return-point memory, realizing multiple memories of asymmetric driving. This reveals a general principle for designing systems that store sequences of cyclic driving, whether symmetric or asymmetric. In disordered systems, asymmetric driving is a sensitive tool for the direct measurement of frustration.

Science & Technology - Other Topics↗
DOE OSTI2014

Compiler-Assisted Detection of Transient Memory Errors

The probability of bit flips in hardware memory systems is projected to increase significantly as memory systems continue to scale in size and complexity. Effective hardware-based error detection and correction requires that the complete data path, involving all parts of the memory system, be protected with sufficient redundancy. First, this may be costly to employ on commodity computing platforms and second, even on high-end systems, protection against multi-bit errors may be lacking. Therefore, augmenting hardware error detection schemes with software techniques is of consider- able interest. In this paper, we consider software-level mechanisms to comprehensively detect transient memory faults. We develop novel compile-time algorithms to instrument application programs with checksum computation codes so as to detect memory errors. Unlike prior approaches that employ checksums on computational and architectural state, our scheme verifies every data access and works by tracking variables as they are produced and consumed. Experimental evaluation demonstrates that the proposed comprehensive error detection solution is viable as a completely software-only scheme. We also demonstrate that with limited hardware support, overheads of error detection can be further reduced.

def-use analysis↗
DOE OSTI2019

PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations

Stencil computation is a classic computational kernel present in many high-performance scientific applications, like image process- ing and partial differential equation solvers (PDE). A stencil compu- tation sweeps over a multi-dimensional grid and repeatedly updates values associated with points using the values from neighboring points. Stencil computations often employ large datasets that ex- ceed cache capacity, leading to excessive accesses to the memory subsystem. As such, 3D stencil computations on large grid sizes are memory-bound. In this paper we present PIMS, an in-memory accelerator for stencil computations. PIMS, implemented in the logic layer of a 3D- stacked memory, exploits the high bandwidth provided by through- silicon vias to reduce redundant memory traffic. Our comprehensive evaluation using three different grid sizes with six categories of orders indicate that the proposed architecture reduces 48.25% of data movement on average and obtains up to 65.55% of bank conflict reduction.

Li, Jie↗
DOE OSTI2023

HBMax: Optimizing Memory Efficiency for Parallel Influence Maximization on Multicore Architectures

The goal of influence maximization is to select k most-influential vertices or seeds in a network, where influence is defined by a given diffusion process. The problem has a number of important applications such as viral marketing, information spread, and epidemic control. Although computing optimal seed set is NP-Hard, due to the submodular nature of the problem efficient approximation algorithms exist. However, even state-of-the-art parallel implementations are limited by a sampling step that incurs large memory footprints. This in turn limits the problem size reach and approximation quality. In this work, we study the memory footprint of the sampling process collecting reverse reachability information in the IMM algorithm over large real-world social networks. We present an adaptive and memory-efficient optimization approach for a state-of-the-art multi-threaded parallel influence maximization algorithm. Our approach,HuffMax, uses a portion of the reverse reachable (RR) sets collected by the algorithm to learn the characteristics of the graph. Then, it compresses the intermediate reverse reachability information with Huffman coding, and queries directly on the compressed data to preserve the memory savings obtained through compression. We also propose an efficient sampling strategy based on the distribution of RR sets, which can further reduce the computation time for typical social networks with long-tail distributions. Considering a NUMA architecture, we scale up our solution on 128-core CPUs and reduce the memory footprint by up to 45.7% with negligible time overhead (or even faster) and without perceivable loss of accuracy.

Chen, Xinyu↗
DOE OSTI2026

The Memory Scaling of Reverse-Mode Differentiation in Particle Accelerator Simulations with Space Charge

The recent development of differentiable simulation codes for particle accelerators has enabled gradient-based workflows that promise finer control and more realistic modeling of accelerator facilities. However, when using reverse-mode automatic differentiation, the memory usage continuously increases during the simulation, and can potentially exceed the available hardware memory - especially when costly space charge computation is included. To study the memory requirements for differentiable simulations, we have implemented space charge in Cheetah, a PyTorch-based beam tracking code that supports reverse-mode differentiation. We find that the memory usage for reverse-mode differentiation grows linearly with the number of macroparticles and cells, and that it is proportional to the number of space charge kicks involved in the simulation. This general scaling can be used to evaluate whether a given differentiable simulation is feasible given hardware memory constraints.

Dhamrait, Arjun↗
DOE OSTI2017

Simplified Interface to Complex Memory Hierarchies 1.x

Memory systems are expected to get evermore complicated in the coming years, and it isn't clear exactly what form that complexity will take. On the software side, a simple, flexible way of identifying and working with memory pools is needed. Additionally, most developers seek code portability and do not want to learn the intricacies of complex memory. Hence, we believe that a library for interacting with complex memory systems should expose two kinds of abstraction: First, a low-level, mechanism-based interface designed for the runtime or advanced user that wants complete control, with its focus on simplified representation but with all decisions left to the caller. Second, a high-level, policy-based interface designed for ease of use for the application developer, in which we aim for best-practice decisions based on application intent. We have developed such a library, called SICM: Simplified Interface to Complex Memory.

Lang, Michael↗
DOE OSTI2021

Preexisting memory CD4 + T cells contribute to the primary response in an HIV-1 vaccine trial

Naive and memory CD4 + T cells reactive with human immunodeficiency virus type 1 (HIV-1) are detectable in unexposed, unimmunized individuals. The contribution of preexisting CD4 + T cells to a primary immune response was investigated in 20 HIV-1–seronegative volunteers vaccinated with an HIV-1 envelope (Env) plasmid DNA prime and recombinant modified vaccinia virus Ankara (MVA) boost in the HVTN 106 vaccine trial (clinicaltrials.gov NCT02296541). Prevaccination naive or memory CD4 + T cell responses directed against peptide epitopes in Env were identified in 14 individuals. After priming with DNA, 40% (8/20) of the elicited responses matched epitopes detected in the corresponding preimmunization memory repertoires, and clonotypes were shared before and after vaccination in 2 representative volunteers. In contrast, there were no shared epitope specificities between the preimmunization memory compartment and responses detected after boosting with recombinant MVA expressing a heterologous Env. Preexisting memory CD4 + T cells therefore shape the early immune response to vaccination with a previously unencountered HIV-1 antigen.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2024

UMap: An application-oriented user level memory mapping library

Exploiting the prominent role of complex memories in exascale node architecture, the UMap page fault handler offers new capabilities to access large memory-mapped data sets directly. UMap provides flexible configuration options to customize page handling to each application, including analysis of massive observational and simulation data sets. The high-performance design features I/O decoupling, dynamic load balancing, and application-level controls. Page faults triggered by application threads and processes accessing data mapped to a UMapp’ed region are handled via the Linux userfaultfd protocol, an asynchronous message-oriented kernel-user communication mechanism that avoids the context switch penalty of traditional signal fault handlers. UMap is fully open source. In this paper, we give an overview of the UMap library architecture, its extensible plugin architecture, and the use/performance of UMap in emerging heterogeneous memory hierarchies such as near-node Non-volatile Memory (NVM) and network attached memories. We highlight new capabilities in two pagefault management plugins, the NetworkStore and SparseStore. We demonstrate the integration between UMap and multiple ECP products including Caliper, Metall, ZFP, Mochi, and Ripples.

97 MATHEMATICS AND COMPUTING↗