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At least 451 records · Page 25

Fuzzy Logic Trajectory Design and Guidance for Terminal Area Energy Management

The second generation reusable launch vehicle will leverage many new technologies to make flight to low earth orbit safer and more cost effective. One important capability will be completely autonomous flight during reentry and landing, thus making it unnecessary to man the vehicle for cargo missions with stringent weight constraints. Implementation of sophisticated new guidance and control methods will enable the vehicle to return to earth under less than favorable conditions. The return to earth consists of three phases--Entry, Terminal Area Energy Management (TAEM), and Approach and Landing. The Space Shuttle is programmed to fly all three phases of flight automatically, and under normal circumstances the astronaut-pilot takes manual control only during the Approach and Landing phase. The automatic control algorithms used in the Shuttle for TAEM and Approach and Landing have been developed over the past 30 years. They are computationally efficient, and based on careful study of the spacecraft's flight dynamics, and heuristic reasoning. The gliding return trajectory is planned prior to the mission, and only minor adjustments are made during flight for perturbations in the vehicle energy state. With the advent of the X-33 and X-34 technology demonstration vehicles, several authors investigated implementing advanced control methods to provide autonomous real-time design of gliding return trajectories thus enhancing the ability of the vehicle to adjust to unusual energy states. The bulk of work published to date deals primarily with the approach and landing phase of flight where changes in heading angle are small, and range to the runway is monotonically decreasing. These benign flight conditions allow for model simplification and fairly straightforward optimization. This project focuses on the TAEM phase of flight where mathematically precise methods have produced limited results. Fuzzy Logic methods are used to make onboard autonomous gliding return trajectory design robust to a wider energy envelope, and the possibility of control surface failures, thus increasing the flexibility of unmanned gliding recovery and landing.

Burchett, Bradley↗

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

Abdeldayem, Hossin↗

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

Armstrong, C. Duane↗

Evolution of the Baseline ISS ECLSS Technologies: The Next Logical Steps

The baseline Environmental Control and Life Support Systems which are currently deployed on the International Space Station or planned to be launched in Node 3 are based on technologies selected in the early 1990's. While they are generally meeting or exceeding requirements for supporting the ISS crew, lessons learned from years of on orbit and ground testing, new advances in technology state of the art, and requirements for future manned missions prompt consideration of the next logical step to enhance these systems to increase performance, robustness, reliability, and reduce on-orbit and logistical resource requirements. This paper discusses the current state of the art in ISS ECLSS technologies, and possible areas for enhancement/improvement. Potential utilization of the ISS as a testbed for on-orbit checkout of selected technology improvements is also addressed.

Carrasquillo, Robyn L.↗

A Numerical Optimization Approach for Tuning Fuzzy Logic Controllers

This paper develops a method to tune fuzzy controllers using numerical optimization. The main attribute of this approach is that it allows fuzzy logic controllers to be tuned to achieve global performance requirements. Furthermore, this approach allows design constraints to be implemented during the tuning process. The method tunes the controller by parameterizing the membership functions for error, change-in-error and control output. The resulting parameters form a design vector which is iteratively changed to minimize an objective function. The minimal objective function results in an optimal performance of the system. A spacecraft mounted science instrument line-of-sight pointing control is used to demonstrate results.

Woodard, Stanley E.↗

Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

Neudeck, Philip G.↗

The ANMLite Language and Logic for Specifying Planning Problems

We present the basic concepts of the ANMLite planning language. We discuss various aspects of specifying a plan in terms of constraints and checking the existence of a solution with the help of a model checker. The constructs of the ANMLite language have been kept as simple as possible in order to reduce complexity and simplify the verification problem. We illustrate the language with a specification of the space shuttle crew activity model that was constructed under the Spacecraft Autonomy for Vehicles and Habitats (SAVH) project. The main purpose of this study was to explore the implications of choosing a robust logic behind the specification of constraints, rather than simply proposing a new planning language.

Butler, Ricky W.↗

Tri-state logic circuit

A line driver including a pair of complementary transistors having their conduction paths serially connected between an operating and a reference potential and their bases connected through a first switch to a signal input terminal. A second switch is connected between the common base connection and the common connection of the conduction paths. With the second switch open and the first closed, an output voltage, responsive to the input signal, corresponding to first or second binary values is obtained. When the second switch is closed and the first opened, the transistor pair is turned off, disconnecting the line driver from its load, thereby providing tri-state logic operation.

Pryor, Richard Lee↗

Deep Space Network Antenna Logic Controller

The Antenna Logic Controller (ALC) software controls and monitors the motion control equipment of the 4,000-metric-ton structure of the Deep Space Network 70-meter antenna. This program coordinates the control of 42 hydraulic pumps, while monitoring several interlocks for personnel and equipment safety. Remote operation of the ALC runs via the Antenna Monitor & Control (AMC) computer, which orchestrates the tracking functions of the entire antenna. This software provides a graphical user interface for local control, monitoring, and identification of faults as well as, at a high level, providing for the digital control of the axis brakes so that the servo of the AMC may control the motion of the antenna. Specific functions of the ALC also include routines for startup in cold weather, controlled shutdown for both normal and fault situations, and pump switching on failure. The increased monitoring, the ability to trend key performance characteristics, the improved fault detection and recovery, the centralization of all control at a single panel, and the simplification of the user interface have all reduced the required workforce to run 70-meter antennas. The ALC also increases the antenna availability by reducing the time required to start up the antenna, to diagnose faults, and by providing additional insight into the performance of key parameters that aid in preventive maintenance to avoid key element failure. The ALC User Display (AUD) is a graphical user interface with hierarchical display structure, which provides high-level status information to the operation of the ALC, as well as detailed information for virtually all aspects of the ALC via drill-down displays. The operational status of an item, be it a function or assembly, is shown in the higher-level display. By pressing the item on the display screen, a new screen opens to show more detail of the function/assembly. Navigation tools and the map button allow immediate access to all screens.

Ahlstrom, Harlow↗

Testing First-Order Logic Axioms in AutoCert

AutoCert [2] is a formal verification tool for machine generated code in safety critical domains, such as aerospace control code generated from MathWorks Real-Time Workshop. AutoCert uses Automated Theorem Provers (ATPs) [5] based on First-Order Logic (FOL) to formally verify safety and functional correctness properties of the code. These ATPs try to build proofs based on user provided domain-specific axioms, which can be arbitrary First-Order Formulas (FOFs). These axioms are the most crucial part of the trusted base, since proofs can be submitted to a proof checker removing the need to trust the prover and AutoCert itself plays the part of checking the code generator. However, formulating axioms correctly (i.e. precisely as the user had really intended) is non-trivial in practice. The challenge of axiomatization arise from several dimensions. First, the domain knowledge has its own complexity. AutoCert has been used to verify mathematical requirements on navigation software that carries out various geometric coordinate transformations involving matrices and quaternions. Axiomatic theories for such constructs are complex enough that mistakes are not uncommon. Second, adjusting axioms for ATPs can add even more complexity. The axioms frequently need to be modified in order to have them in a form suitable for use with ATPs. Such modifications tend to obscure the axioms further. Thirdly, speculating validity of the axioms from the output of existing ATPs is very hard since theorem provers typically do not give any examples or counterexamples.

Ahn, Ki Yung↗

Using Spare Logic Resources To Create Dynamic Test Points

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

Katz, Richard↗

Microhard MHX2420 Orbital Performance Evaluation Using RT Logic T400CS

RT Logic allows simulation of Ground Station - satellite communications: Static tests have been successful. Dynamic tests have been performed for simple passes. Future dynamic tests are needed to simulate real orbit communications. Satellite attitude changes antenna gain. Atmospheric and rain losses need to be added. STK Plug-in will be the next step to improve the dynamic tests. There is a possibility of running longer simulations. Simulation of different losses available in the STK Plug-in. Microhard optimization: Effect of Microhard settings on the data throughput have been understood. Optimized settings improve data throughput for LEO communications. Longer hop intervals make transfer of larger packets more efficient (more time between hops in frequency). Use of FEC (Reed-Solomon) reduces the number of retransmissions for long-range or noisy communications.

TintoreGazulla, Oriol↗

Vertical Navigation Control Laws and Logic for the Next Generation Air Transportation System

A vertical navigation (VNAV) outer-loop control system was developed to capture and track the vertical path segments of energy-efficient trajectories that are being developed for high-density operations in the evolving Next Generation Air Transportation System (NextGen). The VNAV control system has a speed-on-elevator control mode to pitch the aircraft for tracking a calibrated airspeed (CAS) or Mach number profile and a path control mode for tracking the VNAV altitude profile. Mode control logic was developed for engagement of either the speed or path control modes. The control system will level the aircraft to prevent it from flying through a constraint altitude. A stability analysis was performed that showed that the gain and phase margins of the VNAV control system significantly exceeded the design gain and phase margins. The system performance was assessed using a six-deg-of-freedom non-linear transport aircraft simulation and the performance is illustrated with time-history plots of recorded simulation data.

Hueschen, Richard M.↗

Logic Model Checking of Time-Periodic Real-Time Systems

In this paper we report on the work we performed to extend the logic model checker SPIN with built-in support for the verification of periodic, real-time embedded software systems, as commonly used in aircraft, automobiles, and spacecraft. We first extended the SPIN verification algorithms to model priority based scheduling policies. Next, we added a library to support the modeling of periodic tasks. This library was used in a recent application of the SPIN model checker to verify the engine control software of an automobile, to study the feasibility of software triggers for unintended acceleration events.

software analysis↗

DAIDALUS: Detect and Avoid Alerting Logic for Unmanned Systems

This paper presents DAIDALUS (Detect and Avoid Alerting Logic for Unmanned Systems), a reference implementation of a detect and avoid concept intended to support the integration of Unmanned Aircraft Systems into civil airspace. DAIDALUS consists of self-separation and alerting algorithms that provide situational awareness to UAS remote pilots. These algorithms have been formally specified in a mathematical notation and verified for correctness in an interactive theorem prover. The software implementation has been verified against the formal models and validated against multiple stressing cases jointly developed by the US Air Force Research Laboratory, MIT Lincoln Laboratory, and NASA. The DAIDALUS reference implementation is currently under consideration for inclusion in the appendices to the Minimum Operational Performance Standards for Unmanned Aircraft Systems presently being developed by RTCA Special Committee 228.

Munoz, Cesar↗

Near-Field Heat Transfer Enabled Nanothermomechanical Memory and Logic Devices

A thermomechanical memory/logic device is disclosed. In embodiments, the thermomechanical device includes a first thermally controlled terminal (e.g., hot terminal); a second thermally controlled terminal (e.g., cool terminal/base); a stem or other structure that can be thermally expanded connected to the cool terminal; and a thermal conductive head coupled to the stem. The head can exchange heat with the hot terminal. The stem and head are between the first thermally controlled terminal and the second thermally controlled terminal, wherein the stem expands or contracts in response to heat absorbed or given off by the thermal conductive head, causing the head to move towards the first thermally controlled terminal or towards the second thermally controlled terminal until a stable state is reached. For example, bistable thermal states can be used to implement logic states (e.g., ZERO or ONE states).

Ndao, Sidy↗

Runtime Verification Logics A Language Design Perspective

Runtime Verification is a light-weight approach to systems verification, where actual executions of a system are processed and analyzed using rigorous techniques. In this paper we shall narrow the term’s definition to represent the commonly studied variant consisting of verifying that a single system execution conforms to a specification written in a formal specification language. Runtime verification (in this sense) can be used for writing test oracles during testing when the system is too complex for full formal verification, or it can be used during deployment of the system as part of a fault protection strategy, where corrective actions may be taken in case the specification is violated. Specification languages for runtime verification appear to differ from for example temporal logics applied in model checking, in part due to the focus on monitoring of events that carry data, and specifically due to the desire to relate data values existing at different time points, resulting in new challenges in both the complexity of the monitoring approach and the expressiveness of languages. Over the recent years, numerous runtime verification specification languages have emerged, each with its different features and levels of expressiveness and usability. This paper presents an overview and a discussion of this design space.

Reger, Giles↗