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At least 451 records · Page 25

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Peters, Christopher J.↗

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Peters, Christopher J.↗

A Schottky Tune Meter for the Fermilab Mu2E Delivery Ring

The Mu2E experiment will measure the ratio of the rate of the neutrinoless, coherent conversion of muons into electrons as a measure of Charged Lepton Flavor Violation. As part of the Mu2E experiment, a proton storage ring, called the Delivery Ring, will utilize resonant extraction to slow-spill protons to the experiment. To regulate and optimize the Delivery Ring resonant extraction process, a fast tune measurement scheme will be required. This Mu2E tune meter will measure the average tune and the tune spectrum, in multiple time slices, through the entire resonant extraction cycle of nominally 43 msec. The Mu2E tune meter system utilizes vertical and horizontal 21.4 MHz Schottky detector resonant pickups, taken from the decommissioned Tevatron, high-gain amplifiers and digital down-conversion FPGA logic for its signal processing. This paper will present the design of this Schottky tune meter as well as tune measurements from the Mu2E delivery ring.

43 PARTICLE ACCELERATORS↗

Payload/orbiter signal processing and data handling system evaluation presentation

It is recommended that standard digital and along interfaces be adopted. These include: (1) define interfaces compatible with NASA/DOD/industry-accepted design standards; (2) investigate costs of modifying orbiter sybsystem interfaces, (3) investigate cost of designing attached payload interface unit for NASA and commercial payloads and (4) investigate costs of designing interface circuits that can be incorporated into each payload design.

Source record↗

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Real-time Enhancement, Registration, and Fusion for an Enhanced Vision System

Over the last few years NASA Langley Research Center (LaRC) has been developing an Enhanced Vision System (EVS) to aid pilots while flying in poor visibility conditions. The EVS captures imagery using two infrared video cameras. The cameras are placed in an enclosure that is mounted and flown forward-looking underneath the NASA LaRC ARIES 757 aircraft. The data streams from the cameras are processed in real-time and displayed on monitors on-board the aircraft. With proper processing the camera system can provide better-than-human-observed imagery particularly during poor visibility conditions. However, to obtain this goal requires several different stages of processing including enhancement, registration, and fusion, and specialized processing hardware for real-time performance. We are using a real-time implementation of the Retinex algorithm for image enhancement, affine transformations for registration, and weighted sums to perform fusion. All of the algorithms are executed on a single TI DM642 digital signal processor (DSP) clocked at 720 MHz. The image processing components were added to the EVS system, tested, and demonstrated during flight tests in August and September of 2005. In this paper we briefly discuss the EVS image processing hardware and algorithms. We then discuss implementation issues and show examples of the results obtained during flight tests.

Hines, Glenn D.↗

On Convergence of Development Costs and Cost Models for Complex Spaceflight Instrument Electronics

Development costs of a few recent spaceflight instrument electrical and electronics subsystems have diverged from respective heritage cost model predictions. The cost models used are Grass Roots, Price-H and Parametric Model. These cost models originated in the military and industry around 1970 and were successfully adopted and patched by NASA on a mission-by-mission basis for years. However, the complexity of new instruments recently changed rapidly by orders of magnitude. This is most obvious in the complexity of representative spaceflight instrument electronics' data system. It is now required to perform intermediate processing of digitized data apart from conventional processing of science phenomenon signals from multiple detectors. This involves on-board instrument formatting of computational operands from row data for example, images), multi-million operations per second on large volumes of data in reconfigurable hardware (in addition to processing on a general purpose imbedded or standalone instrument flight computer), as well as making decisions for on-board system adaptation and resource reconfiguration. The instrument data system is now tasked to perform more functions, such as forming packets and instrument-level data compression of more than one data stream, which are traditionally performed by the spacecraft command and data handling system. It is furthermore required that the electronics box for new complex instruments is developed for one-digit watt power consumption, small size and that it is light-weight, and delivers super-computing capabilities. The conflict between the actual development cost of newer complex instruments and its electronics components' heritage cost model predictions seems to be irreconcilable. This conflict and an approach to its resolution are addressed in this paper by determining the complexity parameters, complexity index, and their use in enhanced cost model.

Kizhner, Semion↗

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗

Digital Multicasting of Multiple Audio Streams

The Mission Control Center Voice Over Internet Protocol (MCC VOIP) system (see figure) comprises hardware and software that effect simultaneous, nearly real-time transmission of as many as 14 different audio streams to authorized listeners via the MCC intranet and/or the Internet. The original version of the MCC VOIP system was conceived to enable flight-support personnel located in offices outside a spacecraft mission control center to monitor audio loops within the mission control center. Different versions of the MCC VOIP system could be used for a variety of public and commercial purposes - for example, to enable members of the general public to monitor one or more NASA audio streams through their home computers, to enable air-traffic supervisors to monitor communication between airline pilots and air-traffic controllers in training, and to monitor conferences among brokers in a stock exchange. At the transmitting end, the audio-distribution process begins with feeding the audio signals to analog-to-digital converters. The resulting digital streams are sent through the MCC intranet, using a user datagram protocol (UDP), to a server that converts them to encrypted data packets. The encrypted data packets are then routed to the personal computers of authorized users by use of multicasting techniques. The total data-processing load on the portion of the system upstream of and including the encryption server is the total load imposed by all of the audio streams being encoded, regardless of the number of the listeners or the number of streams being monitored concurrently by the listeners. The personal computer of a user authorized to listen is equipped with special- purpose MCC audio-player software. When the user launches the program, the user is prompted to provide identification and a password. In one of two access- control provisions, the program is hard-coded to validate the user s identity and password against a list maintained on a domain-controller computer at the MCC. In the other access-control provision, the program verifies that the user is authorized to have access to the audio streams. Once both access-control checks are completed, the audio software presents a graphical display that includes audiostream-selection buttons and volume-control sliders. The user can select all or any subset of the available audio streams and can adjust the volume of each stream independently of that of the other streams. The audio-player program spawns a "read" process for the selected stream(s). The spawned process sends, to the router(s), a "multicast-join" request for the selected streams. The router(s) responds to the request by sending the encrypted multicast packets to the spawned process. The spawned process receives the encrypted multicast packets and sends a decryption packet to audio-driver software. As the volume or muting features are changed by the user, interrupts are sent to the spawned process to change the corresponding attributes sent to the audio-driver software. The total latency of this system - that is, the total time from the origination of the audio signals to generation of sound at a listener s computer - lies between four and six seconds.

Macha, Mitchell↗

System for Processing Coded OFDM Under Doppler and Fading

An advanced communication system has been proposed for transmitting and receiving coded digital data conveyed as a form of quadrature amplitude modulation (QAM) on orthogonal frequency-division multiplexing (OFDM) signals in the presence of such adverse propagation-channel effects as large dynamic Doppler shifts and frequency-selective multipath fading. Such adverse channel effects are typical of data communications between mobile units or between mobile and stationary units (e.g., telemetric transmissions from aircraft to ground stations). The proposed system incorporates novel signal processing techniques intended to reduce the losses associated with adverse channel effects while maintaining compatibility with the high-speed physical layer specifications defined for wireless local area networks (LANs) as the standard 802.11a of the Institute of Electrical and Electronics Engineers (IEEE 802.11a). OFDM is a multi-carrier modulation technique that is widely used for wireless transmission of data in LANs and in metropolitan area networks (MANs). OFDM has been adopted in IEEE 802.11a and some other industry standards because it affords robust performance under frequency-selective fading. However, its intrinsic frequency-diversity feature is highly sensitive to synchronization errors; this sensitivity poses a challenge to preserve coherence between the component subcarriers of an OFDM system in order to avoid intercarrier interference in the presence of large dynamic Doppler shifts as well as frequency-selective fading. As a result, heretofore, the use of OFDM has been limited primarily to applications involving small or zero Doppler shifts. The proposed system includes a digital coherent OFDM communication system that would utilize enhanced 802.1la-compatible signal-processing algorithms to overcome effects of frequency-selective fading and large dynamic Doppler shifts. The overall transceiver design would implement a two-frequency-channel architecture (see figure) that would afford frequency diversity for reducing the adverse effects of multipath fading. By using parallel concatenated convolutional codes (also known as Turbo codes) across the dual-channel and advanced OFDM signal processing within each channel, the proposed system is intended to achieve at least an order of magnitude improvement in received signal-to-noise ratio under adverse channel effects while preserving spectral efficiency.

Tsou, Haiping↗

Low-Cutoff, High-Pass Digital Filtering of Neural Signals

The figure depicts the major functional blocks of a system, now undergoing development, for conditioning neural signals acquired by electrodes implanted in a brain. The overall functions to be performed by this system can be summarized as preamplification, multiplexing, digitization, and high-pass filtering. Other systems under development for recording neural signals typically contain resistor-capacitor analog low-pass filters characterized by cutoff frequencies in the vicinity of 100 Hz. In the application for which this system is being developed, there is a requirement for a cutoff frequency of 5 Hz. Because the resistors needed to obtain such a low cutoff frequency would be impractically large, it was decided to perform low-pass filtering by use of digital rather than analog circuitry. In addition, it was decided to timemultiplex the digitized signals from the multiple input channels into a single stream of data in a single output channel. The signal in each input channel is first processed by a preamplifier having a voltage gain of approximately 50. Embedded in each preamplifier is a low-pass anti-aliasing filter having a cutoff frequency of approximately 10 kHz. The anti-aliasing filters make it possible to couple the outputs of the preamplifiers to the input ports of a multiplexer. The output of the multiplexer is a single stream of time-multiplexed samples of analog signals. This stream is processed by a main differential amplifier, the output of which is sent to an analog-to-digital converter (ADC). The output of the ADC is sent to a digital signal processor (DSP).

Mojarradi,Mohammad↗

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗

Eight-Bit-Slice GaAs General Processor Circuit

Novel GaAs 8-bit slice enables quick and efficient implementation of variety of fast GaAs digital systems ranging from central processing units of computers to special-purpose processors for communications and signal-processing applications. With GaAs 8-bit slice, designers quickly configure and test hearts of many digital systems that demand fast complex arithmetic, fast and sufficient register storage, efficient multiplexing and routing of data words, and ease of control.

Weissman, John↗

Rotating turbine blade pyrometer

Non-contacting pyrometer system optically measures surface temperature distribution on rotating turbine blade, comprising line-by-line scan via fiber optic probe. Each scan line output is converted to digital signals, temporarily stored in buffer memory, and then processed in minicomputer for display as temperature.

Buchele, D. R.↗

Evaluation of NASA speech encoder

Techniques developed by NASA for spaceflight instrumentation were used in the design of a quantizer for speech-decoding. Computer simulation of the actions of the quantizer was tested with synthesized and real speech signals. Results were evaluated by a phometician. Topics discussed include the relationship between the number of quantizer levels and the required sampling rate; reconstruction of signals; digital filtering; speech recording, sampling, and storage, and processing results.

Source record↗

Aliasing as noise - A quantitative and qualitative assessment

We present a model-based argument that, for the purposes of system design and digital image processing, aliasing should be treated as signal-dependent additive noise. By using a computational simulation based on this model, we process (high resolution images of) natural scenes in a way which enables the 'aliased component' of the reconstructed image to be isolated unambiguously. We demonstrate that our model-based argument leads naturally to system design metrics which quantify the extent of aliasing. And, by illustrating several aliased component images, we provide a qualitative assessment of aliasing as noise.

Park, Stephen K.↗

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

Gerber, Scott S.↗