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All sources NASA NTRS DOE OSTI

DOE OSTI2021

Fast convolutional neural networks on FPGAs with hls4ml

We introduce an automated tool for deploying ultra low-latency, low-power deep neural networks with convolutional layers on field-programmable gate arrays (FPGAs). By extending the hls4ml library, we demonstrate an inference latency of 5 µs using convolutional architectures, targeting microsecond latency applications like those at the CERN Large Hadron Collider. Considering benchmark models trained on the Street View House Numbers Dataset, we demonstrate various methods for model compression in order to fit the computational constraints of a typical FPGA device used in trigger and data acquisition systems of particle detectors. In particular, we discuss pruning and quantization-aware training, and demonstrate how resource utilization can be significantly reduced with little to no loss in model accuracy. We show that the FPGA critical resource consumption can be reduced by 97% with zero loss in model accuracy, and by 99% when tolerating a 6% accuracy degradation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2016

Optical Breath Gas Extravehicular Activity Sensor for the Advanced Portable Life Support System

The function of the infrared gas transducer used during extravehicular activity (EVA) in the current space suit is to measure and report the concentration of carbon dioxide (CO2) in the ventilation loop. The next generation portable life support system (PLSS) requires highly accurate CO2 sensing technology with performance beyond that presently in use on the International Space Station extravehicular mobility unit (EMU). Further, that accuracy needs to be provided over the full operating pressure range of the suit (3 to 25 psia). Accommodation within space suits demands that optical sensors meet stringent size, weight, and power requirements. A laser diode (LD) sensor based on infrared absorption spectroscopy is being developed for this purpose by Vista Photonics, Inc. Version 1.0 prototype devices were delivered to NASA Johnson Space Center (JSC) in September 2011. The prototypes were upgraded with more sophisticated communications and faster response times to version 2.0 and delivered to JSC in July 2012. The sensors incorporate a laser diode based CO2 channel that also includes an incidental water vapor (humidity) measurement. The prototypes are controlled digitally with an field-programmable gate array microcontroller architecture. Based on the results of the iterative instrument development, further prototype development and testing of instruments were performed leveraging the lessons learned where feasible. The present development extends and upgrades the earlier hardware for the advanced PLSS 2.5 prototypes for testing at JSC. The prototypes provide significantly enhanced accuracy for water vapor measurement and eliminate wavelength drift affecting the earlier versions. Various improvements to the electronics and gas sampling are currently being advanced including the companion development of engineering development units that will ultimately be capable of radiation tolerance. The combination of low power electronics with the performance of a long wavelength laser spectrometer enables multi-gas sensors with significantly increased performance over that presently offered in the EMU.

Wood, William R.↗

NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗

NASA NTRS2012

Goldstone Solar System Radar Waveform Generator

Due to distances and relative motions among the transmitter, target object, and receiver, the time-base between any transmitted and received signal will undergo distortion. Pre-distortion of the transmitted signal to compensate for this time-base distortion allows reception of an undistorted signal. In most radar applications, an arbitrary waveform generator (AWG) would be used to store the pre-calculated waveform and then play back this waveform during transmission. The Goldstone Solar System Radar (GSSR), however, has transmission durations that exceed the available memory storage of such a device. A waveform generator capable of real-time pre-distortion of a radar waveform to a given time-base distortion function is needed. To pre-distort the transmitted signal, both the baseband radar waveform and the RF carrier must be modified. In the GSSR, this occurs at the up-conversion mixing stage to an intermediate frequency (IF). A programmable oscillator (PO) is used to generate the IF along with a time-varying phase component that matches the time-base distortion of the RF carrier. This serves as the IF input to the waveform generator where it is mixed with a baseband radar waveform whose time-base has been distorted to match the given time-base distortion function producing the modulated IF output. An error control feedback loop is used to precisely control the time-base distortion of the baseband waveform, allowing its real-time generation. The waveform generator produces IF modulated radar waveforms whose time-base has been pre-distorted to match a given arbitrary function. The following waveforms are supported: continuous wave (CW), frequency hopped (FH), binary phase code (BPC), and linear frequency modulation (LFM). The waveform generator takes as input an IF with a time varying phase component that matches the time-base distortion of the carrier. The waveform generator supports interconnection with deep-space network (DSN) timing and frequency standards, and is controlled through a 1 Gb/s Ethernet UDP/IP interface. This real-time generation of a timebase distorted radar waveform for continuous transmission in a planetary radar is a unique capability.

Quirk, Kevin J.↗

NASA NTRS1975

Automatic computer controlled testing of spacecraft and experiments

Autotest is a flexible, fully automatic, programmable test system. It is externally controlled by a mnemonic test language. Once started, tests can run to completion without further manual intervention. Autotest can be operated manually as well as in automatic mode. Autotest can be adapted to a wide variety of test requirements. Though originally designed to test the Atmosphere Explorer (AE) spacecraft and experiments, autotest can easily be modified to test any electronic device suitable for automated computer testing.

Blakeslee, W. D.↗

DOE OSTI2022

Memory forensic analysis of a programmable logic controller in industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLCs) are used to automate physical processes such as nuclear plants and power grid stations, and are often subject to cyber attacks. As in conventional IT domain, the memory analysis of the PLCs can help answer important forensic questions about the attack, such as the presence of malicious firmware, injection of modified control logic (the program running on the PLC), and manipulation of I/O devices (e.g., sensors and actuators). Unlike conventional IT domain, PLCs have heterogeneous hardware architecture, proprietary firmware and control software, making it challenging to employ a unified framework for their memory forensics. For merely extracting artifacts of forensic importance, reverse-engineering the firmware is a tedious task, and the effort needs to be repeated for every PLC model. As a community, a step-wise approach to tackle this challenge is to analyze the memory of specific PLCs, and subsequently find a generic framework applicable to all PLCs. Our work is a step forward in this direction. By following a methodology that focuses on the functional layer of PLCs instead of reverse engineering the firmware, we analyze the digital forensic artifacts available in a common PLC, Allen-Bradley ControlLogix 1756-L61. Before diving into the memory dump, we analyze the PLC control software to create a list of important artifacts that are sure to exist in the PLC memory dump. The approach employs a setup where PLC control software RSLogix-5000 is connected to the PLC, and the memory dump can be obtained as and when needed. We create test cases that sequentially highlight each category of artifacts, followed by an examination of the resultant impact on memory. After attaining the listed artifacts, we employ conventional string and known data searches to extract interesting information present in this PLC's memory. The memory analysis profile, presented as a Python library and shared with the community, can help a forensic investigator to readily extract forensic artifacts from the same model's controller. The adopted approach may help researchers in creating memory profile of other PLCs, and ultimately formulating a generic PLC memory analysis framework.

Rais, Muhammad Haris↗

NASA NTRS1998

Refurbishment and Automation of Thermal Vacuum Facilities at NASA/GSFC

The thermal vacuum facilities located at the Goddard Space Flight Center (GSFC) have supported both manned and unmanned space flight since the 1960s. Of the eleven facilities, currently ten of the systems are scheduled for refurbishment or replacement as part of a five-year implementation. Expected return on investment includes the reduction in test schedules, improvements in safety of facility operations, and reduction in the personnel support required for a test. Additionally, GSFC will become a global resource renowned for expertise in thermal engineering, mechanical engineering, and for the automation of thermal vacuum facilities and tests. Automation of the thermal vacuum facilities includes the utilization of Programmable Logic Controllers (PLCs), the use of Supervisory Control and Data Acquisition (SCADA) systems, and the development of a centralized Test Data Management System. These components allow the computer control and automation of mechanical components such as valves and pumps. The project of refurbishment and automation began in 1996 and has resulted in complete computer control of one facility (Facility 281), and the integration of electronically controlled devices and PLCs in multiple others.

Dunn, Jamie↗

NASA NTRS1999

Refurbishment and Automation of Thermal Vacuum Facilities at NASA/GSFC

Dunn, Jamie↗

DOE OSTI2022

A DNA molecular printer capable of programmable positioning and patterning in two dimensions

Nanoscale manipulation and patterning usually require costly and sensitive top-down techniques such as those used in scanning probe microscopies or in semiconductor lithography. DNA nanotechnology enables exploration of bottom-up fabrication and has previously been used to design self-assembling components capable of linear and rotary motion. In this work, we combine three independently controllable DNA origami linear actuators to create a nanoscale robotic printer. The two-axis positioning mechanism comprises a moveable gantry, running on parallel rails, threading a mobile sleeve. We show that the device is capable of reversibly positioning a write head over a canvas through the addition of signaling oligonucleotides. We demonstrate “write” functionality by using the head to catalyze a local DNA strand–exchange reaction, selectively modifying pixels on a canvas. Furthermore, this work demonstrates the power of DNA nanotechnology for creating nanoscale robotic components and could find application in surface manufacturing, biophysical studies, and templated chemistry.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

DOE OSTI2023

Fabrication of Large-Area Metal-on-Carbon Catalytic Condensers for Programmable Catalysis

Catalytic condensers stabilize charge on either side of a high-k dielectric film to modulate the electronic states of a catalytic layer for the electronic control of surface reactions. Here, carbon sputtering provided for fast, large-scale fabrication of metal–carbon catalytic condensers required for industrial application. Carbon films were sputtered on HfO 2 dielectric/p-type Si with different thicknesses (1, 3, 6, and 10 nm), and the enhancement of conductance and capacitance of carbon films was observed upon increasing the carbon thickness following thermal treatment at 400 °C. After Pt deposition on the carbon films, the Pt catalytic condenser exhibited a high capacitance of ∼210 nF/cm 2 that was maintained at a frequency ∼1000 Hz, satisfying the requirement for a dynamic catalyst to implement catalytic resonance. Temperature-programmed desorption of carbon monoxide yielded CO desorption peaks that shifted in temperature with the varying potential applied to the condenser (−6 or +6 V), indicating a shift in the binding energy of carbon monoxide on the Pt condenser surface. A substantial increase in capacitance (∼2000 nF/cm 2 ) of the Pt-on-carbon devices was observed at elevated temperatures of 400 °C that can modulate ∼10% of charge per metal atom when 10 V potential was applied. A large catalytic condenser of 42 cm 2 area Pt/C/HfO 2 /Si exhibited a high capacitance of 9393 nF with a low leakage current/capacitive current ratio (<0.1), demonstrating the practicality and versatility of the facile, large-scale fabrication method for metal–carbon catalytic condensers.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

NASA NTRS2011

SNE Industrial Fieldbus Interface

Programmable logic controllers (PLCs) have very limited diagnostic and no prognostic capabilities, while current smart sensor designs do not have the capability to communicate over Fieldbus networks. The aim is to interface smart sensors with PLCs so that health and status information, such as failure mode identification and measurement tolerance, can be communicated via an industrial Fieldbus such as ControlNet. The SNE Industrial Fieldbus Interface (SIFI) is an embedded device that acts as a communication module in a networked smart sensor. The purpose is to enable a smart sensor to communicate health and status information to other devices, such as PLCs, via an industrial Fieldbus networking protocol. The SNE (Smart Network Element) is attached to a commercial off-the-shelf Any bus-S interface module through the SIFI. Numerous Anybus-S modules are available, each one designed to interface with a specific Fieldbus. Development of the SIFI focused on communications using the ControlNet protocol, but any of the Anybus-S modules can be used. The SIFI communicates with the Any-bus module via a data buffer and mailbox system on the Anybus module, and supplies power to the module. The Anybus module transmits and receives data on the Fieldbus using the proper protocol. The SIFI is intended to be connected to other existing SNE modules in order to monitor the health and status of a transducer. The SIFI can also monitor aspects of its own health using an onboard watchdog timer and voltage monitors. The SIFI also has the hardware to drive a touchscreen LCD (liquid crystal display) unit for manual configuration and status monitoring.

Lucena, Angel↗

DOE OSTI2025

A Novel Protection Scheme for Unbalanced Faults in Inverter Dominated Networks: A Computationally Efficient Algorithm for Entry-Level Relays

Microgrids are now a common practice in distribution systems to increase resilience and reliability. However, microgrid protection remains a critical challenge, considering its requirement to operate in both grid connected and islanded, and the variability in fault characteristics under each mode of operation. This paper presents unbalanced power (S unb ) based fault detection algorithm, which considers local voltage and current unbalances to determine faults in the system. S unb is a computationally efficient fault detection algorithm that is suitable for implementation in the programmable logic of entry level protective relays. In addition, the difference in current and voltage unbalance (D n ) is used to determine the fault type. The proposed method demonstrates high sensitivity and selectivity for line-to-ground (LG), line-to-line (LL), and double line-to-ground (LLG) faults, representing the most common faults in distribution systems. It also allows relay coordination with upstream and downstream protection devices in both island and grid connected operation, while preserving grading margins. The same pickup and time multiplier settings of a particular relay for both modes of operation eliminates the need for adaptive settings, which rely on communication networks. Validation was performed with a hardware-in-the-loop (HIL) setup using Typhoon HIL real time simulator interfaced with three entry-level, SEL 751 relays. Results confirmed the algorithm’s ability to discriminate fault conditions, and determine the fault type under both operating modes, maintain fast detection times, and ensure proper protection coordination.

fault classification↗

NASA NTRS1992

JPL activities on development of acousto-optic tunable filter imaging spectrometer

Recent activities of JPL in the development of a new type of imaging spectrometers for earth observation and planetary exploration are reported. This instrument uses the acousto-optic tunable filter (AOTF) as high resolution and fast programmable bandpass filter. AOTF operates in the principle of acousto-optic interaction in an anisotropic medium. This filter can be tuned in sequential, random, and multiwavelength access modes, providing observational flexibility. The diffraction process in the filter generates two diffracted monochromatic beams with polarization orthogonal to each other, creating a unique capability to measure both polarimetric and spectral properties of the incoming light simultaneously with a single instrument. The device gives wide wavelength operations with reasonably large throughput. In addition, it is in a compact solid-state structure without moving parts, providing system reliability. These attractive features give promising opportunities to develop a new generation of airborne/spaceborne and ground, real-time, imaging spectrometer systems for remote sensing applications.

Cheng, Li-Jen↗

NASA NTRS1976

Selective data segment monitoring system

High speed data monitoring apparatus is described for displaying the bit pattern of a selected portion of a block of transmitted data comprising a shift register for receiving the transmitted data and for temporarily containing the consecutive data bits. A programmable sync detector for monitoring the contents of the shift register and for generating a sync signal when the shift register contains a predetermined sync code is included. A counter is described for counting the data bits input to the shift register after the sync signal is generated and for generating a count complete signal when a selected number of data bits have been input to the register. A data storage device is used for storing the contents of the shift register at the time the count complete signal is generated.

Wirth, M. N.↗

DOE OSTI2024

Experimental Examination of Additively Manufactured Patterns on Structural Nuclear Materials for Digital Image Correlation Strain Measurements

Abstract Background There are a limited number of commercially available sensors for monitoring the deformation of materials in-situ during harsh environment applications, such as those found in the nuclear and aerospace industries. Such sensing devices, including weldable strain gauges, extensometers, and linear variable differential transformers, can be destructive to material surfaces being investigated and typically require relatively large surface areas to attach (> 10 mm in length). Digital image correlation (DIC) is a viable, non-contact alternative to in-situ strain deformation. However, it often requires implementing artificial patterns using splattering techniques, which are difficult to reproduce. Objective Additive manufacturing capabilities offer consistent patterns using programmable fabrication methods. Methods In this work, a variety of small-scale periodic patterns with different geometries were printed directly on structural nuclear materials (i.e., stainless steel and aluminum tensile specimens) using an aerosol jet printer (AJP). Unlike other additive manufacturing techniques, AJP offers the advantage of materials selection. DIC was used to track and correlate strain to alternative measurement methods during cyclic loading, and tensile tests (up to 1100 µɛ) at room temperature. Results The results confirmed AJP has better control of pattern parameters for small fields of view and facilitate the ability of DIC algorithms to adequately process patterns with periodicity. More specifically, the printed 100 μm spaced dot and 150 μm spaced line patterns provided accurate measurements with a maximum error of less than 2% and 4% on aluminum samples when compared to an extensometer and commercially available strain gauges. Conclusion Our results highlight a new pattern fabrication technique that is form factor friendly for digital image correlation in nuclear applications.

Novich, K. A. (ORCID:0000000204466022)↗

NASA NTRS2013

An Offload NIC for NASA, NLR, and Grid Computing

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

Awrach, James↗

DOE OSTI2025

Leveraging dendritic complexity for neuromorphic computing

Abstract Beyond-von Neumann computing approaches are necessary to sustain the growth of microelectronics and the increasing appetite for artificial intelligence/machine learning algorithms. Neuromorphic computing is an emerging paradigm that takes inspiration from the brain to provide a path forward to improve the computational efficiency and computational density of next-generation computing architectures. In nature, we observe brains performing complex computations with a much smaller energy footprint than conventional computing approaches. Current neuromorphic systems are focused primarily on scalability, namely, increasing the number of computational units (neurons) and connections between units (synapses). However, for brain-like cognition and efficiency in next-generation computing hardware, we need increased complexity in function, as well as improved connection density for scalability. Here, we present our work that aims to incorporate dendrites for ‘compute-on-wire’ in neuromorphic architectures to increase the computational complexity (e.g. number of programmable parameters, nonlinear dynamics) as well as computational efficiency (energy/compute) of artificial neural networks (ANNs). We do this by showcasing neuromorphic dendrite elements that can be leveraged for various applications. We will present examples of neuroscience-inspired direction-selective circuits and an ANN with active dendrites leveraging shunting inhibition. We also demonstrate the benefits of using dendrites in deep neural networks. To conclude, we discuss how we can utilize emerging hardware devices in these systems and design next-generation neuromorphic architectures with dendrites.

Cardwell, Suma G. (ORCID:0000000226575545)↗

NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗