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At least 433 records · Page 24

High-Level Simulation for Spiking Neuromorphic Computing Systems

Neuromorphic computing systems are alternatives to conventional microprocessors, often built from unconventional hardware. Designing and evaluating these systems requires multiple levels of simulation, from the device level to the circuit level to the system level. In this paper, we describe the system level simulator of a neuromorphic computing system based on memristors. We compare it to a circuit level simulator of the same system, both verifying its accuracy and demonstrating its performance improvement. We argue that system level simulation is an essential part of the design process of neuromorphic systems.

Skuda, Nicholas↗

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗

Development of a Hybrid Single/Two-Phase Capillary-Based Micro-Cooler using Copper Inverse Opals Wick with Silicon 3D Manifold for High-Heat-Flux Cooling Application

Previously, we reported two-phase capillary-based cooling using narrow (200 to 1000 ..mu..m) heater bridge copper inverse opal (CIO) wicks with heat flux level of 1400 Wcm -2 and superheat ~ 10 degrees C. Here, we demonstrate the area scaling of the proposed technology to a large-area micro-cooler for high-heat-flux cooling of microprocessors and power electronics. We developed a hybrid single/two-phase micro-cooler that relies on capillary-wicking in a 25-..mu..m-thick CIO with an open silicon microchannel 3D-manifold for liquid delivery and vapor extraction, achieving a high heat flux ~ 400 Wcm -2 over a heated area of 10 x 10 mm 2 . For a range of inlet water flowrates from 5 to 60 g(min) -1 , we achieved total thermal resistances and vapor qualities of 0.68 cm 2 degrees CW -1 to 0.2 cm 2 degrees CW -1 and 0.55 to 0.12, respectively. The flowrates are 10x smaller than those of conventional single- or two-phase microchannel cooling technology. The corresponding two-phase thermal resistances ranges from 0.05 to 0.02 cm 2 degrees CW -1 with temperature superheat of 8 to 6 degrees C, respectively. While the overall performance of the large-area (10 x 10 mm 2 ) capillary-based micro-cooler degraded compared to the previous demonstration of the technology for a heated area of 5 x 5 mm 2 , however, preliminary CFD modeling indicates that an improved manifold design will be able to achieve comparable performance.

capillary flow↗

Accelerated Architectures Create Programming Opportunities

In the early 2000s, industry switched to multicore microprocessors to address semiconductors' speed and power limits. However, the change was unsuccessful, leading to dire claims that “Moore's law is ending.” In conclusion, this column suggests that while the approach was sound, it needed a deeper architectural transformation. Industry has since discovered a suitable architecture, but work remains on software to support it.

97 MATHEMATICS AND COMPUTING↗

ByzSec — A Multi-layered Byzantine Resilient Architecture for Bulk Power System Protective Relays

Reliability, selectivity, and sensitivity are the fundamental attributes of any protection system, acting as the main drivers in the selection of schemes, and equipment. In high-voltage systems, microprocessor-based relays represent the industry’s preferred solution, providing engineers with a vast array of benefits. However, they remain vulnerable to cybersecurity events that may compromise their functionality. To help mitigate against potential cybersecurity risks, this paper presents a fault-tolerant, Byzantine Resilient (BR) architecture that significantly increases the cybersecurity attributes of a protection system while minimizing the amount of performance impacts and integration overheads introduced. The solution relies on an array of independent relays that utilize robust consensus methods (based on Spire [1], [2]) to ensure correct system behavior is achieved even when a relay has been compromised. Furthermore, the solution has been complemented with a custom-built Situational Awareness engine that can be used to detect and identify potential threats. The implemented solution has been developed in consultation with three hardware vendors and has been tested to comply with the performance requirements of a 345kV differential protection scheme (87T). The results indicate that the proposed architecture is a comprehensive solution that: supports the strict correctness and performance requirements of the bulk power grid while providing a cost-effective alternative that offers a seamless, long-term solution.

byzantine security, Fault Tolerant Application Sof↗

Development and Evaluation of a Cost-Effective Behind-the-Meter Synchronized Measurement Unit for Enhanced Grid Integration

This paper presents the development of the Inverter Based Resource Monitor (IBRM), an innovative behind-the-meter synchronized measurement unit (SMU) tailored for integration with inverter-based resources (IBRs). The IBRM distinguishes itself as a highly accurate and cost-effective SMU, offering facile deployment and connectivity to IBRs. It is equipped to conduct real-time voltage and current waveform analyses, serving as a phasor measurement unit (PMU) with exceptionally rapid synchrophasor transmission capabilities. The device incorporates a cutting-edge dual-core architecture designed to minimize sampling delays inherent to its microprocessor, thereby enhancing the precision of synchronized waveform measurements. Moreover, the IBRM is adept at recording high-fidelity waveform data, capturing nuances such as waveform distortions, high-order harmonics, and wide-band oscillations prevalent in power grids with substantial IBR presence. A prototype of the IBRM has been constructed and subjected to rigorous testing to assess its functional capabilities and measurement precision, utilizing both idealized signal generators and a real-world off-grid inverter setup as benchmarks.

Wu, Ori [ORNL] (ORCID:0000000326723410)↗

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗

Identifying the Root Causes of Wait States in Large-Scale Parallel Applications

Driven by growing application requirements and accelerated by current trends in microprocessor design, the number of processor cores on modern supercomputers is increasing from generation to generation. However, load or communication imbalance prevents many codes from taking advantage of the available parallelism, as delays of single processes may spread wait states across the entire machine. Moreover, when employing complex point-to-point communication patterns, wait states may propagate along far-reaching cause-effect chains that are hard to track manually and that complicate an assessment of the actual costs of an imbalance. Building on earlier work by Meira Jr. et al., we present a scalable approach that identifies program wait states and attributes their costs in terms of resource waste to their original cause. Ultimately, by replaying event traces in parallel both forward and backward, we can identify the processes and call paths responsible for the most severe imbalances even for runs with hundreds of thousands of processes.

97 MATHEMATICS AND COMPUTING↗

C3PU:Real-Time Predictive Charge Control Software for Battery Management Systems (Code for Charge Control and Predictive Unit) [SWR-21-48]

C3PU sets up a model predictive control formulation for the optimal charging control of battery packs and can be deployed for real-time operation on an embedded microprocessor. C3PU uses electrochemical and thermal models of battery packs to predict the charging trajectories of the battery pack over a time horizon under different operating conditions. It then selects the optimal charging trajectory such that a pre-defined objective is minimized, which in the present state of the code is to minimize the charging duration of the battery pack. The optimal charging trajectory is obtained by solving an underlying mathematical problem. However, C3PU is flexible to incorporate other charging objectives. The underlying battery models can be swapped as well, as long as they follow certain mathematical properties. Mathematically, optimal control problems (in this case, optimally controlling the charging current of the battery pack) are computationally expensive. C3PU implements advanced numerical techniques, namely pseudo-spectral optimization, to reduce the computational burden of the underlying problem to solve. This allows for the problem to be solved in real-time in an embedded system. Once the optimal charging trajectory is computed over a time horizon, C3PU can package such data and send it out via appropriate communication protocols.

Mishra, Partha↗

Image Processing Occupancy Sensor

The Image Processing Occupancy Sensor, or IPOS, is a novel sensor technology developed at the National Renewable Energy Laboratory (NREL). The sensor is based on low-cost embedded microprocessors widely used by the smartphone industry and leverages mature open-source computer vision software libraries. Compared to traditional passive infrared and ultrasonic-based motion sensors currently used for occupancy detection, IPOS has shown the potential for improved accuracy and a richer set of feedback signals for occupant-optimized lighting, daylighting, temperature setback, ventilation control, and other occupancy and location-based uses. Unlike traditional passive infrared (PIR) or ultrasonic occupancy sensors, which infer occupancy based only on motion, IPOS uses digital image-based analysis to detect and classify various aspects of occupancy, including the presence of occupants regardless of motion, their number, location, and activity levels of occupants, as well as the illuminance properties of the monitored space. The IPOS software leverages the recent availability of low-cost embedded computing platforms, computer vision software libraries, and camera elements.

Source record↗

Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance to megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration board exhibits radiation resilience to over 200 krad. Furthermore, our ASIC microprocessor using RHBD techniques was shown to be fully functional after an exposure of 2.5 Mrad whereas the COTS microcontroller units failed catastrophically at <100 krad. The methods developed in this work can facilitate the long-term viability of radiation-hard robotic systems, thereby avoiding obsolescence issues. As a case in point, the nuclear industry with its low purchasing power does not drive the semiconductor industry strategic plans, and the rapid advancements in electronics technology can leave legacy systems stranded.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Multi-Angle Snowflake Camera Value-Added Product

The Multi-Angle Snowflake Camera (MASC) addresses a need for high-resolution multi-angle imaging of hydrometeors in freefall with simultaneous measurement of fallspeed. As illustrated in Figure 1, the MASC consists of three cameras, separated by 36°, each pointing at an identical focal point approximately 10 cm away. Located immediately above each camera, a light aims directly at the center of depth of field for its corresponding camera. The focal point at which the cameras are aimed lies within a ring through which hydrometeors fall. The ring houses a system of near-infrared emitter-detector pairs, arranged in two arrays separated vertically by 32 mm. When hydrometeors pass through the lower array, they simultaneously trigger all cameras and lights. Fallspeed is calculated from the time it takes to traverse the distance between the upper and lower triggering arrays. The trigger electronics filter out ambient light fluctuations associated with varying sunlight and shadows. The microprocessor onboard the MASC controls the camera system and communicates with the personal computer (PC). The image data is sent via FireWire 800 line, and fallspeed (and camera control) is sent via a Universal Serial Bus (USB) line that relies on RS232-over-USB serial conversion. See Table 1 for specific details on the MASC located at the Oliktok Point Mobile Facility on the North Slope of Alaska. The value-added product (VAP) detailed in this documentation analyzes the raw data (Section 2.0) using Python: images rely on OpenCV image processing library and derived aggregated statistics rely on some clever averaging. See Sections 4.1 and 4.2 for more details on what variables are computed.

47 OTHER INSTRUMENTATION↗

Watchdog Project

The Watchdog Project completed 100% of the project Statement of Project Objective (SOPO). The Watchdog project was a very aggressive project looking to accomplish commercialization of technology that had never been commercialized, as a result it took six years to complete not the original three that were planned. No additional federal funds were requested from the original proposal and SEL contributed the additional cost share required to complete the project. The result of the Watchdog Project is the world’s first industrial rated Software Defined Network (SDN) switch commercially available. This technology achieved the SOPOO and DOE Roadmap goals to have strong network access control, improve reliability and network performance, and give the asset owner the ability to minimize attack surface before and during an attack. The Watchdog project is an alliance between CenterPoint Energy Houston Electric, Pacific Northwest National Laboratories (PNNL), and Schweitzer Engineering Laboratories, Inc. (SEL). SEL is the world’s leader in microprocessor-based electronic equipment for protecting electric power systems. PNNL performs basic and applied research to deliver energy, environmental, and national security for our nation. CenterPoint Energy is the third largest publicly traded natural gas delivery company in the U.S and third largest combined electricity and natural gas delivery company. The Watchdog Project efforts were combined with the SDN Project efforts to produce the entire SDN system solution for the critical infrastructure. The Watchdog project addresses Topic Area of Interest 5: Secure Communications, for the DEFOA- 0000359 by protecting the control system local area network itself and the communications coming from and going to the electronic devices on the local network. Local area networks usually are not routed and have little or no filtering capabilities. Combine this with the fact control system protocols are designed with inherent trust the control system owners have very little choice on how to protect communications on the local network. The Watchdog project reduces security risks in electric sector control system local area networks (LANs) by providing: Network access control (NAC) Multi-Layer firewall (physical through transport layer) Containment of malware or unauthorized traffic spreading across the network White list protocols and application message types filtering Configurable, proactive traffic engineering The Watchdog project achieved all of the above by developing an SDN switch.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Cryogenic Frostpoint Hygrometer (CFH) Instrument Handbook

The U.S. Department of Energy (DOE) Atmospheric Radiation Measurement (ARM) Climate Research Facility’s Cryogenic Frostpoint Hygrometer (CFH) is a small, balloon-borne instrument that provides highly accurate measurements of water vapor in the atmosphere. The CFH, although highly modified, is based upon the National Oceanic and Atmospheric Administration (NOAA)/Climate Monitoring and Diagnostic Laboratory (CMDL) frostpoint hygrometer (FPH) that has been flown in Boulder, Colorado, since 1980. The CFH has a significantly greater sensitivity to water vapor than standard radiosondes, as it can measure the frostpoint or dewpoint temperatures at an accuracy better than 0.2 K corresponding to water volume mixing ratios accuracies of only a few parts per million. The main instrument part is a small mirror, which is cooled by a cryogen in order to be covered with a thin layer of water vapor condensate. A pair of photodiodes detects the condensation on the temperature-controlled mirror. The phase of the condensate is controlled by a force-freezing algorithm, allowing for clear interpretation of the dew point versus frostpoint. The replacement of analog electronics with a microprocessor, a feedback controller, and thermistor calibration have led to improved accuracy and performance of the CFH over its predecessors. Further characteristics like reduced power consumption and low instrument weight made the CFH a successful instrument to perform in situ balloon-borne measurements of water vapor in the upper troposphere and lower stratosphere. CFH measurements are now used worldwide to validate radiosonde, satellite, and ground-based profiler measurements.

47 OTHER INSTRUMENTATION↗

Assessment of Commercial-Off-The-Shelf Electronics for use in a Short-Term Geostationary Satellite

Commercial-Off-The-Shelf (COTS) electronics offer cutting-edge capability at lower prices compared to their space-grade counterparts. However, their use in space missions has been limited due to concerns around survivability in a space environment; COTS devices are not designed to survive the harsh radiation environment of space. Nonetheless, for space missions with short durations it may be possible to use COTS electronics. This study evaluates the use of several families of COTS electronics for a specific short-term mission. An assembled database including selected space grade and COTS components is discussed. High confidence FPGAs, microprocessors, and optocouplers COTS are identified. Medium confidence Memory, ADCs, DACs, power electronics, and RFMMICs COTS are also included, as well as testing to improve confidence in medium confidence parts. An experimental approach for evaluating tin whisker susceptibility for tin-leaded COTS components is described. Using COTS electronics in Short-Term Geostationary Satellites is feasible; this report includes enabling tools.

42 ENGINEERING↗

Comparative Assessment of Experimental Testing of Instrument with an Embedded Digital Device Using Model-Based and Conventional Methods

The use of digital equipment has not been widespread in U.S. nuclear facilities. A major contributing factor to this situation arises from regulatory concerns about common cause failures (CCFs) stemming from the use of identical software in redundant systems, questions as to how to quantify the reliability of software-based products, validity of tools that are used for software verification and validation (V&V), and the effectiveness of software QA procedures. Compounding the concerns are sporadic incidents of digital equipment malfunctions in nuclear power plants, including lockups resulting from software memory leaks, feedwater control malfunctions due to excessive traffic on Ethernet networks, software logic errors, and other problems leading to plant trips. Additionally, the limited amount of demonstrated research and a lack of industry consensus on quantitative software reliability methodologies has hindered the widespread adoption of digital I&C in the nuclear industry. In a recent Regulatory Issue Summary (RIS), the U.S. Nuclear Regulatory Commission (NRC) identified concerns about the impact of greater use of instrumentation and control (I&C) equipment with an embedded digital device (EDD) [1]. Specifically, the NRC staff states that increased use of such devices “may increase a facility’s vulnerability to a CCF” (i.e., common-cause failure). The prevailing NRC guidance regarding software CCF (SCCF) identifies two design attributes that are acceptable for eliminating CCF concerns: (1) diversity or (2) testability (specifically, 100% testability). Either solution can result in high costs and remaining licensing uncertainty (i.e., how much diversity is enough? how to ensure test coverage of every possible sequence of device states?). Consequently, many utilities and reactor designers have limited or avoided more extensive use of digital technology to minimize licensing, scheduling, and financial risk. Without development of cost effective qualification methods to satisfy regulatory requirements and address the potential for CCF vulnerability associated with EDDs, the nuclear power industry may not be able to realize the benefits of digital technology achieved by other industries. In order to address these challenges, the U.S. Department of Energy (DOE) is sponsoring this research to assess the prospect of CCF in digital I&C equipment. The purpose of the current research is to develop an effective approach employing science-based methods to resolve concerns about CCF vulnerability that serve to inhibit deployment of advanced instrumentation (e.g., sensors, actuators, microcontrollers) with EDDs in nuclear power applications. The research objectives address the challenge of establishing high levels of safety and reliability assurance needed for the qualification of EDDs (e.g., microprocessors, programmable logic devices) that are subject to software design faults, complex failure modes, and CCF vulnerability. Specific objectives are: (1) assess the regulatory context for treatment of CCF vulnerability a graded approach to their qualification, (3) develop and extend model-based testing methods to enable effective demonstration of whether devices are subject to CCF, which may arise from vulnerabilities introduced at any stage of the design lifecycle, (4) establish a cost-effective testing framework that incorporates automation and test scenario prioritization, and (5) demonstrate the qualification approach through selection and testing of candidate digital device(s). This report documents an assessment of the results from experimental testing of a representative instrument with an embedded digital device. The experiment serves as a proof-of-concept demonstration of a model-based testing (MBT) framework. The objective of MBT is to ensure that an EDD undergoes suitably comprehensive testing to establish that it is not subject to SCCF. The approach by which MBT accomplishes this objective is through development and application of an effective test suite that provides the appropriate coverage to detect the full range of postulated faults that may arise at the requirements, design, and code (implementation) level of the EDD software. The findings of the experiment involve the application of the MBT framework by Ohio State University (OSU) through testing of the selected demonstration instrument (i.e., the prototype smart pressure sensor developed by Virginia Commonwealth University, VCU). In addition, the experiment findings also involve application of a more conventional black-box testing approach that serves as a baseline against which the MBT methodology can be compared. The primary outcome documented in this report is the comparative analysis of the capabilities demonstrated for each method. The results of the analysis demonstrate clear benefits that arise from the MBT methodology. The comparison indicates greater effectiveness from the more comprehensive evidence available through MBT and enhanced efficiency achieved through automation within the MBT framework. The structure of the report addresses the approach and application of each test method as well as the comparative analysis of the experimental results. Chapter 2 gives a summary overview of the demonstration approach. Chapter 3 covers the baseline testing and Chapter 4 documents the model-based testing. Chapter 5 describes the findings of the comparative analysis and presents the conclusions that can be drawn about the effectiveness and efficiency of the MBT methodology.

47 OTHER INSTRUMENTATION↗

Post Moore's Law Report

Moore's law is driving an information revolution, worldwide economic growth, and is a tool for national security. This report explains how dire proclamations that "Moore's law is ending" are due to a natural redefinition of the phrase, but computing remains positioned to both drive economic growth and support national security. The computer industry used to be led by the semiconductor companies that made ever faster microprocessors with larger memories. However, control is shifting to new ways of designing computers, notably based on 3D chips and new analog and digital architectures. While artificial intelligence and quantum computing research have become mainstream pursuits, these latter two areas seem destined split off from Moore's law rather than become a part of it. We include a discussion of recent developments and opportunities in optical communications and computing.

97 MATHEMATICS AND COMPUTING↗

Improving the performance of medical imaging applications using SYCL

As opposed to the Open Computing Language (OpenCL) programming model, in which host and device codes are generally written in different programming languages, SYCL can combine host and device codes for an application in a type-safe way to improve development productivity and performance portability. Hence, this report shows the experimental results of applying the SYCL programming model to medical imaging applications for a study on performance portability and programming productivity between OpenCL and SYCL. Rodinia is a widely used open-source benchmark suite for heterogeneous computing. We choose two medical imaging applications (Heart Wall and Particle Filter) in the benchmark suite, migrate the OpenCL implementations of the applications to the SYCL implementations, and evaluate their performance and productivity on Intel® microprocessors that contain a central processing unit (CPU) and an integrated graphics processing unit (GPU). The maturing SYCL compilers, which are based on a conformant implementation of the SYCL 1.2.1 Khronos specification, have been actively optimized for Intel® computing platforms. The experimental results are promising in terms of the raw performance and productivity. Although the SYCL implementation of the Heart Wall application does not execute successfully on a CPU, the SYCL implementations of the application can achieve comparable or better performance than the OpenCL implementation on Intel® integrated GPUs. For the Particle Filter application, the performance difference between the SYCL and OpenCL implementations is comparable on the GPUs for most cases, but the SYCL implementations are on average 4X faster than the OpenCL implementations on Intel® Xeon® CPUs. For programming productivity, we arguably use lines of code as a way to measure programming productivity in software. The SYCL programs reduce the lines of code of the OpenCL programs by 52% and 38% for the Heart Wall and Particle Filter, respectively. The results indicate that SYCL is a promising programming model for heterogeneous computing with the maturing compilers. We organize the remainder of the report as follows. Section II introduces the SYCL programming model, compares the major differences between an OpenCL program and a SYCL program, and describes the characteristics of the two applications. Section III describes the SYCL programming model in more details, and shows the SYCL implementation of a kernel function in the Particle Filter application as an example. In Section IV, we evaluate the performance of the applications on the CPUs and GPUs. Section V concludes the report.

59 BASIC BIOLOGICAL SCIENCES↗