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At least 433 records · Page 24

Single event induced transients in I/O devices - A characterization

The results of single-event upset (SEU) testing performed to evaluate the parametric transients, i.e., amplitude and duration, in several I/O devices, and the impact of these transients are discussed. The failure rate of these devices is dependent on the susceptibility of interconnected devices to the resulting transient change in the output of the I/O device. This failure rate, which is a function of the susceptibility of the interconnected device as well as the SEU response of the I/O device itself, may be significantly different from an upset rate calculated without taking these factors into account. The impact at the system level is discussed by way of an example.

Newberry, D. M.↗

Optimized testing of meshes

Efficient testing techniques for two-dimensional mesh interconnection networks are presented. The tests cover faults in the arbitration logic of the switches; this includes an examination of fault detection in the data paths, routing, and control circuitry, including the conflict resolution capabilities of mesh interconnection networks using topological test methods. The proposed methods are not implementation specific and can be applied to any design with a mesh topology. The topology and behavior of the network are described and definitions are presented. The fault model is defined and parallel testing methods for the entire network are given.

Malek, Miroslaw↗

Time variant analysis of large scale constrained rotorcraft systems dynamics - An exploitation of IBM-3090 vector-processor's pipe-lining feature

A generalized algorithmic procedure is presented for handling the constraints in transmissions, which are treated as a multibody system of interconnected rigid/flexible bodies. The type of constraints are classified based on the interconnection of the bodies, assuming one or more points of contact to exist between them. The method is explained through flow charts and configuration/interaction tables. A significant increase in speed of execution is achieved by vectorizing the developed code in computationally intensive areas. The study of an example consisting of two meshing disks rotating at high angular velocity is carried out. The dynamic behavior of the constraint forces associated with the generalized coordinates of the system are plotted by selecting various modes. Applications are intended for the study of dynamic and subsequent prediction of constraint forces at the gear teeth contacting points in helicopter transmissions with the aim of improving performance dependability.

Amirouche, F. M. L.↗

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗

Flexible, Thin-Film Solar-Cell Blanket

Much of available area used to absorb solar energy. Proposed blanket of solar photovoltaic cells mounted on exterior surface of equipment it powers. Readily conforms to irregular shapes. Does not require separate supporting structure and saves space. Not added on to equipment but constitutes an integral part of it. Interconnection wiring deposited on sheet photolithographically or by other suitable masking/fabrication methods. Complete blanket, including cells and interconnections, fabricated as rigid unit directly on, and supported by, nonplanar surface to be covered.

Stella, Paul M.↗

A Large-Grain Mapping Approach for Multiprocessor Systems Through Data Flow Model Ph.D. Thesis

A large-grain level mapping method is presented of numerical oriented applications onto multiprocessor systems. The method is based on the large-grain data flow representation of the input application and it assumes a general interconnection topology of the multiprocessor system. The large-grain data flow model was used because such representation best exhibits inherited parallelism in many important applications, e.g., CFD models based on partial differential equations can be presented in large-grain data flow format, very effectively. A generalized interconnection topology of the multiprocessor architecture is considered, including such architectural issues as interprocessor communication cost, with the aim to identify the 'best matching' between the application and the multiprocessor structure. The objective is to minimize the total execution time of the input algorithm running on the target system. The mapping strategy consists of the following: (1) large-grain data flow graph generation from the input application using compilation techniques; (2) data flow graph partitioning into basic computation blocks; and (3) physical mapping onto the target multiprocessor using a priority allocation scheme for the computation blocks.

Kim, Hwa-Soo↗

Artificial intelligence approach to planning the robotic assembly of large tetrahedral truss structures

An assembly planner for tetrahedral truss structures is presented. To overcome the difficulties due to the large number of parts, the planner exploits the simplicity and uniformity of the shapes of the parts and the regularity of their interconnection. The planning automation is based on the computational formalism known as production system. The global data base consists of a hexagonal grid representation of the truss structure. This representation captures the regularity of tetrahedral truss structures and their multiple hierarchies. It maps into quadratic grids and can be implemented in a computer by using a two-dimensional array data structure. By maintaining the multiple hierarchies explicitly in the model, the choice of a particular hierarchy is only made when needed, thus allowing a more informed decision. Furthermore, testing the preconditions of the production rules is simple because the patterned way in which the struts are interconnected is incorporated into the topology of the hexagonal grid. A directed graph representation of assembly sequences allows the use of both graph search and backtracking control strategies.

Homemdemello, Luiz S.↗

Superconductivity devices: Commercial use of space

High T sub C superconducting thick film were prepared by a screen printing process. Y-based (YBa2Cu3O(7-x) superconducting thick film were printed on 211/Al2O3, SNT/Al2O3, and YSZ substrates. Because of poor adhesion of the superconductor thick films to 211/Al2O3 and SNT/Al2O3 substrates, relatively low T sub C and J sub C values were obtained from the films printed on these substrates. Critical temperatures (T sub C) of YBa2Cu3O(7-x) thick films deposited on 211/Al2O3 and SNT/Al2O3 substrates were about 80 K. The critical current densities (J sub C) of these films were less than 2 A/sq cm. Higher T sub C and J sub C YBa2Cu3O(7-x) thick films were printed on YSZ substrates. A YBa2Cu3O(7-x) thick film with T sub C=86.4 and J sub C= 50.4 A/sq cm was prepared by printing the film on YSZ substrate and firing at 990 C for 10 minutes. Multiple-lead samples were also prepared on the YSZ substrates. The multiple-lead samples showed lower T sub C and/or J sub C values than those of the plain samples. The electrical properties of YBa2Cu3O(7-x) thick films were determined by the microstructures of the films. The YBa2Cu3O(7-x) thick films printed on the YSZ substrates, which had the best properties among the films printed on the three different kinds of substrates, had the highest density and the best particle interconnection. The YBa2Cu3O(7-x) thick films with preferred orientation in (001) direction were obtained on the YSZ substrates. Cracks, which retard the properties of the films, were found from the films deposited on the YSZ substrates. Currently, a MSZ (Magnesium Stabilized Zirconia) substrate, which had higher thermal expansion coefficient than the YSZ substrate, is used as substrate for the YBa2Cu3O(7-x) thick film in order to eliminate the cracks on the film. Bi-based superconductor thick films were printed on polycrystalline MgO and YSZ substrates. Interactions between BSCCO thick films and the YSZ substrates were observed. Various buffer layer materials were applied onto the substrates in order to avoid the interactions between the BSCCO thick films and the ZrO2-based substrates. So far, a BSCCO printed on MgO substrate with T Sub C=89K was obtained. The J sub C of the film was lower than 0.1 A/sq cm by reason of poor interconnectivity of the BSCCO particles.

Haertling, Gene↗

Scalable Optical-Fiber Communication Networks

Scalable arbitrary fiber extension network (SAFEnet) is conceptual fiber-optic communication network passing digital signals among variety of computers and input/output devices at rates from 200 Mb/s to more than 100 Gb/s. Intended for use with very-high-speed computers and other data-processing and communication systems in which message-passing delays must be kept short. Inherent flexibility makes it possible to match performance of network to computers by optimizing configuration of interconnections. In addition, interconnections made redundant to provide tolerance to faults.

Chow, Edward T.↗

Neurodynamics With Spatial Self-Organization

Report presents theoretical study of dynamics of neural network organizing own response in both phase space and in position space. Postulates several mathematical models of dynamics including spatial derivatives representing local interconnections among neurons. Shows how neural responses propagate via these interconnections and how spatial pattern of neural responses formed in homogeneous biological neural network.

Zak, Michail A.↗

Data distribution satellite

The Data Distribution Satellite (DDS), operating in conjunction with the planned space network, the National Research and Education Network and its commercial derivatives, would play a key role in networking the emerging supercomputing facilities, national archives, academic, industrial, and government institutions. Centrally located over the United States in geostationary orbit, DDS would carry sophisticated on-board switching and make use of advanced antennas to provide an array of special services. Institutions needing continuous high data rate service would be networked together by use of a microwave switching matrix and electronically steered hopping beams. Simultaneously, DDS would use other beams and on board processing to interconnect other institutions with lesser, low rate, intermittent needs. Dedicated links to White Sands and other facilities would enable direct access to space payloads and sensor data. Intersatellite links to a second generation ATDRS, called Advanced Space Data Acquisition and Communications System (ASDACS), would eliminate one satellite hop and enhance controllability of experimental payloads by reducing path delay. Similarly, direct access would be available to the supercomputing facilities and national data archives. Economies with DDS would be derived from its ability to switch high rate facilities amongst users needed. At the same time, having a CONUS view, DDS would interconnect with any institution regardless of how remote. Whether one needed high rate service or low rate service would be immaterial. With the capability to assign resources on demand, DDS will need only carry a portion of the resources needed if dedicated facilities were used. Efficiently switching resources to users as needed, DDS would become a very feasible spacecraft, even though it would tie together the space network, the terrestrial network, remote sites, 1000's of small users, and those few who need very large data links intermittently.

Stevens, Grady H.↗

Applications of satellite technology to broadband ISDN networks

Two satellite architectures for delivering broadband integrated services digital network (B-ISDN) service are evaluated. The first is assumed integral to an existing terrestrial network, and provides complementary services such as interconnects to remote nodes as well as high-rate multicast and broadcast service. The interconnects are at a 155 Mbs rate and are shown as being met with a nonregenerative multibeam satellite having 10-1.5 degree spots. The second satellite architecture focuses on providing private B-ISDN networks as well as acting as a gateway to the public network. This is conceived as being provided by a regenerative multibeam satellite with on-board ATM (asynchronous transfer mode) processing payload. With up to 800 Mbs offered, higher satellite EIRP is required. This is accomplished with 12-0.4 degree hopping beams, covering a total of 110 dwell positions. It is estimated the space segment capital cost for architecture one would be about $190M whereas the second architecture would be about $250M. The net user cost is given for a variety of scenarios, but the cost for 155 Mbs services is shown to be about $15-22/minute for 25 percent system utilization.

Price, Kent M.↗

Efficiently modeling neural networks on massively parallel computers

Neural networks are a very useful tool for analyzing and modeling complex real world systems. Applying neural network simulations to real world problems generally involves large amounts of data and massive amounts of computation. To efficiently handle the computational requirements of large problems, we have implemented at Los Alamos a highly efficient neural network compiler for serial computers, vector computers, vector parallel computers, and fine grain SIMD computers such as the CM-2 connection machine. This paper describes the mapping used by the compiler to implement feed-forward backpropagation neural networks for a SIMD (Single Instruction Multiple Data) architecture parallel computer. Thinking Machines Corporation has benchmarked our code at 1.3 billion interconnects per second (approximately 3 gigaflops) on a 64,000 processor CM-2 connection machine (Singer 1990). This mapping is applicable to other SIMD computers and can be implemented on MIMD computers such as the CM-5 connection machine. Our mapping has virtually no communications overhead with the exception of the communications required for a global summation across the processors (which has a sub-linear runtime growth on the order of O(log(number of processors)). We can efficiently model very large neural networks which have many neurons and interconnects and our mapping can extend to arbitrarily large networks (within memory limitations) by merging the memory space of separate processors with fast adjacent processor interprocessor communications. This paper will consider the simulation of only feed forward neural network although this method is extendable to recurrent networks.

Farber, Robert M.↗

Interfacing a high performance disk array file server to a Gigabit LAN

Our previous prototype, RAID-1, identified several bottlenecks in typical file server architectures. The most important bottleneck was the lack of a high-bandwidth path between disk, memory, and the network. Workstation servers, such as the Sun-4/280, have very slow access to peripherals on busses far from the CPU. For the RAID-2 system, we addressed this problem by designing a crossbar interconnect, Xbus board, that provides a 40MB/s path between disk, memory, and the network interfaces. However, this interconnect does not provide the system CPU with low latency access to control the various interfaces. To provide a high data rate to clients on the network, we were forced to carefully and efficiently design the network software. A block diagram of the system hardware architecture is given. In the following subsections, we describe pieces of the RAID-2 file server hardware that had a significant impact on the design of the network interface.

Seshan, Srinivasan↗

Stochastic architecture for Hopfield neural nets

An expandable stochastic digital architecture for recurrent (Hopfield like) neural networks is proposed. The main features and basic principles of stochastic processing are presented. The stochastic digital architecture is based on a chip with n full interconnected neurons with a pipeline, bit processing structure. For large applications, a flexible way to interconnect many such chips is provided.

Pavel, Sandy↗

Measurements over distributed high performance computing and storage systems

Requirements are carefully described in descriptions of systems to be acquired but often there is no requirement to provide measurements and performance monitoring to ensure that requirements are met over the long term after acceptance. A set of measurements for various UNIX-based systems will be available at the 1992 Goddard Conference on Mass Storage Systems and Technologies. The authors invite others to contribute to the set of measurements. The framework for presenting the measurements of supercomputers, workstations, file servers, mass storage systems, and the networks that interconnect them are given. Production control and database systems are also included. Though other applications and third party software systems are not addressed, it is important to measure them as well. The capability to integrate measurements from all these components from different vendors, and from the third party software systems was recognized and there are efforts to standardize a framework to do this. The measurement activity falls into the domain of management standards. Standards work is ongoing for Open Systems Interconnection (OSI) systems management; AT&T, Digital, and Hewlett-Packard are developing management systems based on this architecture even though it is not finished. Another effort is in the UNIX International Performance Management Working Group. In addition, there are the Open Systems Foundation's Distributed Management Environment and the Object Management Group. A paper comparing the OSI systems management model and the Object Management Group model has been written. The IBM world has had a capability for measurement for various IBM systems since the 1970's and different vendors were able to develop tools for analyzing and viewing these measurements. Since IBM was the only vendor, the user groups were able to lobby IBM for the kinds of measurements needed. In the UNIX world of multiple vendors, a common set of measurements will not be as easy to get.

Williams, Elizabeth↗

A nonsingular model of the open magnetosphere

We present a modified version of the Toffoletto and Hill (1989) open magnetosphere model that incorporates a tail-like interconection field with a discontinuity 10 represent the slow-mode expansion fan that defines the high-latitude tail magnetopause. (The interconnection field is defined as the perturbation on an initially closed magnetosphere model to make it open.) The expansion fan controls the open field line region in the tail, and the intersection of the fan with the tail current sheet is, by design, the x line. The new interconnection field allows greater control of the tail field structure; in particular, it enables us to eliminate the nightside mapping singularity that occurs in previous models when the interplanetary magnetic field is nonsouthward. Also, in contrast to earlier models, the far tail x line extends farther downstream on the flanks than in the center of the tail, consistent with observations.

Toffoletto, F. R.↗

Fast, Massively Parallel Data Processors

Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

Heaton, Robert A.↗