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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Digital controllers for VTOL aircraft

Using linear-optimal estimation and control techniques, digital-adaptive control laws have been designed for a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. Two distinct discrete-time control laws are designed to interface with velocity-command and attitude-command guidance logic, and each incorporates proportional-integral compensation for non-zero-set-point regulation, as well as reduced-order Kalman filters for sensor blending and noise rejection. Adaptation to flight condition is achieved with a novel gain-scheduling method based on correlation and regression analysis. The linear-optimal design approach is found to be a valuable tool in the development of practical multivariable control laws for vehicles which evidence significant coupling and insufficient natural stability.

Stengel, R. F.↗
DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗
NASA NTRS1982

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented.

Lam, A. Y.↗
NASA NTRS1989

Optical Addressing And Clocking Of RAM's

Proposed random-access-memory (RAM) addressing system, in which memory linked optically to read/write logic circuits, greatly increases computer operating speed. System - comprises addressing circuits including numerous lasers as signal sources, numerous optical gates including optical detectors associated with memory cells, and holographic element to direct light signals to desired memory-cell locations - applied to high-capacity digital systems, supercomputers, and complex microcircuits.

Johnston, Alan R.↗
DOE OSTI2026

Polynomial-time preparation of low-temperature Gibbs states for two-dimensional toric code

In this work, we propose a polynomial-time algorithm for preparing the Gibbs state of the two-dimensional toric code Hamiltonian at any temperature, starting from any initial state, significantly improving upon prior estimates that suggested exponential scaling with inverse temperature. We prove that fast mixing at low temperature for the two-dimensional toric code can be achieved by augmenting local jump operators with simple global jump operators, which enable efficient transitions between logical sectors. To establish tight lower bounds on the spectral gap, we introduce a new reduction method that eventually maps the problem to estimating the spectral gap of a perturbed graph Laplacian on a stair graph. Our proof also shows that the Lindblad dynamics with a digitally implemented low-temperature local Davies generator is able to efficiently drive the quantum state toward the ground state manifold.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1975

Digital transmitter for data bus communications system

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

Proch, G. E.↗
NASA NTRS1984

Airstart performance of a digital electronic engine control system on an F100 engine

The digital electronic engine control (DEEC) system installed on an F100 engine in an F-15 aircraft was tested. The DEEC system incorporates a closed-loop air start feature in which the fuel flow is modulated to achieve the desired rate of compressor acceleration. With this logic the DEEC equipped F100 engine can achieve air starts over a larger envelope. The DEEC air start logic, the test program conducted on the F-15, and its results are described.

Burcham, F. W., Jr.↗
NASA NTRS2001

New Data Source for Studying and Modelling the Topside Ionosphere

The existing uncertainties about density profiles in the topside ionosphere, i.e., in the height regime from hmF2 to approx. 2000 km, requires the search for new data sources. Millions of ionograms had been recorded by the ISIS and Alouette satellites in the sixties and seventies, that never were analyzed in terms of electron density profiles. In recent years an effort started to digitize the analog recordings to prepare the ionograms for computerized analysis. This paper shows how the digital ionograms are processed and the electron density profiles (from satellite orbit altitude, 1400 km for ISIS-2, down to the F peak) are calculated. The most difficult part of the task is the automatic scaling of the echo traces in the ISIS ionograms. Unlike the ionograms from modern ionosondes, the ISIS ionograms do not identify the wave polarization of the different echo traces, so physical logic must be applied to identify the ordinary ()) and extraordinary (X) traces, and this is not always successful. Characteristic resonance features seen in the topside ionograms occur at the gyro and plasma frequencies. An elaborate scheme was developed to identify these resonance frequencies in order to determine the local plasma and gyrofrequencies. This information helps in the identification of the O and X traces, and it provides the starting density of the electron density profile. The inversion of the echo traces into electron density profiles uses the same modified Chebyshev polynomial fitting technique that is successfully applied in the ground-based Digisonde network. The automatic topside ionogram scaler with true height algorithm TOPIST is successfully scaling approx. 70% of the ionograms. An 'editing process' is available to manually scale the more difficult ionograms. The home page for the ISIS project is at http://nssdc.gsfc.nasa.gov/space/isis/isis-status.html. It provides access to as of January 2001, 3000,000 digitized ISIS ionogram data and to related software. A search page lets users select data location, time, and a host of other search criteria. The automated processing of the ISIS ionograms will begin later this year and the electron density profiles will be made available from the project home page. The ISIS data restoration efforts are supported through NASA's Applied Systems and Information Research Program.

Huang, Xue-Qin↗
NASA NTRS1981

F-8 digital fly-by-wire aircraft analytic redundancy management flight test experience

The formulation and flight test results of an algorithm to detect and isolate the first failure of any one of twelve duplex control sensors being monitored are described. The technique uses like sensor output differences for fault detection while relying upon analytic redundancy relationships among unlike quantities to isolate the faulty sensor. The fault isolation logic utilizes the modified sequential probability ratio test, which explicitly accommodates the inevitable irreducible low frequency errors present in the analytic redundancy residuals. In addition, the algorithm uses sensor output selftest, which takes advantage of the duplex sensor structure by immediately removing a highly erratic sensor from control calculations and analytic redundancy relationships while awaiting a definitive fault isolation decision via analytic redundancy.

Deckert, J. C.↗
NASA NTRS1967

General purpose computer programs for numerically analyzing linear ac electrical and electronic circuits for steady-state conditions

Digital computer programs determine steady-state performance characteristics of active and passive linear circuits. The ac analysis program solves the basic circuit parameters. The compiler program solves these circuit parameters and in addition provides a more versatile program by allowing the user to perform mathematical and logical operations.

Egebrecht, R. A.↗
NASA NTRS2008

Hardware Architecture Study for NASA's Space Software Defined Radios

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗
NASA NTRS1982

LANDSAT and radar mapping of intrusive rocks in SE-Brazil

The feasibility of intrusive rock mapping was investigated and criteria for regional geological mapping established at the scale of 1:500,00 in polycyclic and polymetamorphic areas using the logic method of photointerpretation of LANDSAT imagery and radar from the RADAMBRASIL project. The spectral behavior of intrusive rocks, was evaluated using the interactive multispectral image analysis system (Image-100). The region of Campos (city) in northern Rio de Janeiro State was selected as the study area and digital imagery processing and pattern recognition techniques were applied. Various maps at the 2:250,000 scale were obtained to evaluate the results of automatic data processing.

Parada, N. D. J.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS1981

Flight test results for the F-8 digital fly-by-wire aircraft control sensor analytic redundancy management technique

This paper reviews the formulation and flight test results of an algorithm to detect and isolate the first failure of any one of twelve duplex control sensor signals being monitored. The technique uses like-signal differences for fault detection while relying upon analytic redundancy relationships among unlike quantities to isolate the faulty sensor. The fault isolation logic utilizes the modified sequential probability ratio test, which explicitly accommodates the inevitable irreducible low frequency errors present in the analytic redundancy residuals. In addition, the algorithm uses sensor output selftest, which takes advantage of the duplex sensor structure by immediately removing a highly erratic sensor from control calculations and analytic redundancy relationships while awaiting a definitive fault isolation decision via analytic redundancy. This study represents a proof of concept demonstration of a methodology that can be applied to duplex or higher flight control sensor configurations and, in addition, can monitor the health of one simplex signal per analytic redundancy relationship.

Deckert, J. C.↗
NASA NTRS1974

Digital adaptive flight control design using single stage model following indices

Simple mechanical linkages are often unable to cope with many control problems associated with high-performance aircraft. This has led to the development of digital fly-by-wire control systems and in particular digital adaptive controllers that can be efficiently adjusted during system operation. To this effect, a control law has been derived based upon the minimization of a single-stage weighted combination of control energy and the squared error between the states of a linear plant and model. This control logic is interfaced with an on-line weighted least-squares estimator and a Kalman state filter. The utility of the resultant control system is illustrated by its application to the linearized dynamics of a typical fighter aircraft.

Alag, G.↗
NASA NTRS1975

Users manual for flight control design programs

Computer programs for the design of analog and digital flight control systems are documented. The program DIGADAPT uses linear-quadratic-gaussian synthesis algorithms in the design of command response controllers and state estimators, and it applies covariance propagation analysis to the selection of sampling intervals for digital systems. Program SCHED executes correlation and regression analyses for the development of gain and trim schedules to be used in open-loop explicit-adaptive control laws. A linear-time-varying simulation of aircraft motions is provided by the program TVHIS, which includes guidance and control logic, as well as models for control actuator dynamics. The programs are coded in FORTRAN and are compiled and executed on both IBM and CDC computers.

Nalbandian, J. Y.↗
NASA NTRS1999

Test Results for the Automated Rendezvous and Capture System

The Automated Rendezvous and Capture (AR&C) system was designed and tested at NASA's Marshall Space Flight Center (MSFC) to demonstrate technologies and mission strategies for automated rendezvous and docking of spacecraft in Earth orbit, The system incorporates some of the latest innovations in Global Positioning, System space navigation, laser sensor technologies and automated mission sequencing algorithms. The system's initial design and integration was completed in 1998 and has undergone testing at MSFC. This paper describes the major components of the AR&C system and presents results from the official system tests performed in MSFC's Flight Robotics Laboratory with digital simulations and hardware in the loop tests. The results show that the AR&C system can safely and reliably perform automated rendezvous and docking missions in the absence of system failures with 100 percent success. When system failures are included, the system uses its automated collision avoidance maneuver logic to recover in a safe manner. The primary objective of the AR&C project is to prove that by designing a safe and robust automated system, mission operations cost can be reduced by decreasing the personnel required for mission design, preflight planning and training required for crewed rendezvous and docking missions.

Cruzen, Craig↗
DOE OSTI2025

Investigating the Vulnerabilities of the Direct Transfer Trip Scheme for Network Protector Units in the Secondary Networks of Electric Power Distribution Grids

Network protector units (NPUs) are crucial parts of the protection of secondary networks to effectively isolate faults occurring on the primary feeders. When a fault occurs on the primary feeder, there is a path of the fault current going through the service transformers that causes a negative flow of current on the NPU connected to the faulted feeder. Conventionally, NPUs rely on the direction of current with respect to the voltage to detect faults and make a correct trip decision. However, the conventional NPU logic does not allow the reverse power flow caused by distributed energy resources installed on secondary networks. The communication-assisted direct transfer trip logic for NPUs can be used to address this challenge. However, the communication-assisted scheme is exposed to some vulnerabilities arising from the disruption or corruption of the communicated data that can endanger the reliable operation of NPUs. This paper evaluates the impact of the malfunction of the communication system on the operation of communication-assisted NPU logic. To this end, the impact of packet modification and denial-of-service cyberattacks on the communication-assisted scheme are evaluated. The evaluation was performed using a hardware-in-the-loop (HIL) co-simulation testbed that includes both real-time power system and communication network digital simulators. This paper evaluates the impact of the cyberattacks for different fault scenarios and provides a list of recommendations to improve the reliability of communication-assisted NPU protection.

direct transfer trip↗