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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Four- and five-layer silicon-clad dielectric waveguides

Computer modeling studies conducted on four-layer silicon-clad dielectric waveguides indicate that the attenuation (alpha) and mode index (beta/K) behave as exponentially damped sinusoids as the silicon thickness is increased. The observed effect can be explained quite simply as a periodic coupling between the guided modes of the lossless structure and the lossy modes supported by the high-refractive index silicon. The attenuation and mode index are significantly altered by conductivity changes in the silicon; an amplitude modulator and an intensity modulator were proposed using these results. Predicted high attenuations in the device may be reduced significantly with a silicon dioxide buffer layer between the semiconductor and the polystyrene guide. Experimental confirmation of the predicted characteristics is still necessary. A number of thin-silicon film waveguides have been RF sputtered but attenuation measurements to verify the damped oscillatory behavior are forthcoming. Conductivity variations of the silicon should demonstrate the modulation capabilities.

Mcwright, G.↗
NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS1985

Crystal growth of device quality GaAs in space

The present program has been aimed at solving the fundamental and technological problems associated with Crystal Growth of Device Quality in Space. The initial stage of the program was devoted strictly to ground-based research. The unsolved problems associated with the growth of bulk GaAs in the presence of gravitational forces were explored. Reliable chemical, structural and electronic characterization methods were developed which would permit the direct relation of the salient materials parameters (particularly those affected by zero gravity conditions) to the electronic characteristics of single crystal GaAs, in turn to device performance. These relationships are essential for the development of optimum approaches and techniques. It was concluded that the findings on elemental semiconductors Ge and Si regarding crystal growth, segregation, chemical composition, defect interactions, and materials properties-electronic properties relationships are not necessarily applicable to GaAs (and to other semiconductor compounds). In many instances totally unexpected relationships were found to prevail.

Gatos, H. C.↗
NASA NTRS2000

A Technique for Rapidly Deploying a Concentration Gradient with Applications to Microgravity

The latter half of the last century has seen rapid advancements in semiconductor crystal growth powered by the demand for high performance electronics in myriad applications. The reduced gravity environment of space has also been used for crystal growth tests, especially in instances where terrestrial growth has largely been unsuccessful. While reduced gravity crystal growth affords some control of the gravity parameter, many crystals grown in space, to date, have structural flaws believed to result from convective motions during the growth phase. The character of these instabilities is not well understood but is associated with thermal and solutal density variations near the solidification interface in the presence of residual gravity and g-jitter. In order to study these instabilities in a separate, controlled space experiment, a concentration gradient would first have to be artificially established in a timely manner as an initial condition. This is generally difficult to accomplish in a microgravity environment because the momentum of the fluid injected into a test cell tends to swirl around and mix in the absence of a restoring force. The use of magnetic fields to control the motion and position of liquids has received growing interest in recent times. The possibility of using the force exerted by a non-uniform magnetic field on a ferrofluid to not only achieve fluid manipulation but also to actively control fluid motion makes it an attractive candidate for space applications. This paper describes a technique for quickly establishing a linear or exponential fluid concentration gradient using a magnetic field in place of gravity to stabilize the deployment. Also discussed is a photometric technique for measuring the concentration profile using light attenuation. Results of the ground-based experiments indicate that the concentration distribution is within 3% of the predicted value. Although any range of concentations can be realized, photometric constraints are discussed which impose some limitations on measurements.

Leslie, Fred↗
NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗
NASA NTRS1986

Direct experimental determination of voltage across high-low junctions

High-low (HL) junctions form a part of many semiconductor devices, including back surface field solar cells. A first experimental determination and interpretation of the voltage across the HL junction under low- and high-injection conditions is presented as a function of the voltage across a nearby p/n junction. Theoretical analysis from first principles is shown to bear well on the experimental results. In addition, a test structure is proposed for measurement of the effective surface recombination velocity at the HL junctions.

Daud, T.↗
NASA NTRS2001

Synthesis of ZnO:As Films Using Off-Axis Sputtering Deposition

As a novel oxide semiconductor material, ZnO is interesting for use in many applications. For fabricating electronic devices, it is important to have n- and p- type ZnO materials. Arsenic has been proven to be one of the p-type dopants for ZnO materials. However, information in studying the ZnAsO ternary compound films has been scarce. In order to investigate the morphology, structure and electrical properties of ZnAsO ternary compounds, ZnO:As films have been synthesized using off-axis sputtering deposition on various substrates including (100) Si and (0001) sapphire crystals. Films are grown under various growth conditions. ZnO:As targets with the atomic weight ratios of arsenic to zinc from 0.01 to 0.10 are used for film synthesis. The growth temperatures and pressures range from 350 to 550C and 5 to 150 mTorr, respectively. Argon to oxygen gas ratio for film growth is varied to examine the film quality as well. Film surface morphology, crystal structure, and compositions, are characterized using atomic force microscopy, x-ray diffraction, and energy dispersive spectroscopy, respectively. The compositions of target material and ZnO:As films grown under various conditions are then assessed. The electrical properties were also measured. The detail of these measurements will be discussed in the presentation.

Zhu, Shen↗
NASA NTRS2003

Using Proteins to Build Nanocomputers

How low can we go? This is the question challenging scientists who want to build ever-smaller electronic components. As famed physicist Richard Feynmann said in 1959, 'there is plenty of room at the bottom,' meaning at the atomic or nanometric scale. But even Feynmann could only guess at how we might eventually build things 'down there.' As current lithographic techniques for etching semiconductor circuits rapidly approach their physical limits, scientists are looking for new and less expensive ways to fabricate circuits at infinitesimally small scales. NASA scientists have discovered a new tool that may help accomplish this goal - proteins. The basic building blocks of life may be harnessed to build computers and sensors on the nanoscale. Proteins provide self-assembling structures that can be engineered to build ordered arrays of quantum dots.

Laufenberg, Larry↗
NASA NTRS2008

Fabricating Nanodots using Lift-Off of a Nanopore Template

A process for fabricating a planar array of dots having characteristic dimensions of the order of several nanometers to several hundred nanometers involves the formation and use of a thin alumina nanopore template on a semiconductor substrate. The dot material is deposited in the nanopores, then the template is lifted off the substrate after the dots have been formed. This process is expected to be a basis for development of other, similar nanofabrication processes for relatively inexpensive mass production of nanometerscale optical, optoelectronic, electronic, and magnetic devices. Alumina nanopore templates are self-organized structures that result from anodization of aluminum under appropriate conditions. Alumina nanopore templates have been regarded as attractive for use in fabricating the devices mentioned above, but prior efforts to use alumina nanopore templates for this purpose have not been successful. One reason for the lack of success is that the aspect ratios (ratios between depth and diameter) of the pores have been too large: large aspect ratios can result in blockage of deposition and/or can prevent successful lift-off. The development of the present process was motivated partly by a requirement to reduce aspect ratios to values (of the order of 10) for which there is little or no blockage of deposition and attempts at lift-off are more likely to be successful. The fabrication process is outlined.

Yang, Eui-Hyeok↗
NASA NTRS2003

Improved Process for Fabricating Carbon Nanotube Probes

An improved process has been developed for the efficient fabrication of carbon nanotube probes for use in atomic-force microscopes (AFMs) and nanomanipulators. Relative to prior nanotube tip production processes, this process offers advantages in alignment of the nanotube on the cantilever and stability of the nanotube's attachment. A procedure has also been developed at Ames that effectively sharpens the multiwalled nanotube, which improves the resolution of the multiwalled nanotube probes and, combined with the greater stability of multiwalled nanotube probes, increases the effective resolution of these probes, making them comparable in resolution to single-walled carbon nanotube probes. The robust attachment derived from this improved fabrication method and the natural strength and resiliency of the nanotube itself produces an AFM probe with an extremely long imaging lifetime. In a longevity test, a nanotube tip imaged a silicon nitride surface for 15 hours without measurable loss of resolution. In contrast, the resolution of conventional silicon probes noticeably begins to degrade within minutes. These carbon nanotube probes have many possible applications in the semiconductor industry, particularly as devices are approaching the nanometer scale and new atomic layer deposition techniques necessitate a higher resolution characterization technique. Previously at Ames, the use of nanotube probes has been demonstrated for imaging photoresist patterns with high aspect ratio. In addition, these tips have been used to analyze Mars simulant dust grains, extremophile protein crystals, and DNA structure.

Stevens, R.↗
NASA NTRS2003

Microscopic Modeling of Intersubband Optical Processes in Type II Semiconductor Quantum Wells: Linear Absorption

Linear absorption spectra arising from intersubband transitions in semiconductor quantum well heterostructures are analyzed using quantum kinetic theory by treating correlations to the first order within Hartree-Fock approximation. The resulting intersubband semiconductor Bloch equations take into account extrinsic dephasing contributions, carrier-longitudinal optical phonon interaction and carrier-interface roughness interaction which is considered with Ando s theory. As input for resonance lineshape calculation, a spurious-states-free 8-band kp Hamiltonian is used, in conjunction with the envelop function approximation, to compute self-consistently the energy subband structure of electrons in type II InAs/AlSb single quantum well structures. We demonstrate the interplay of nonparabolicity and many-body effects in the mid-infrared frequency range for such heterostructures.

Li, Jian-Zhong↗
NASA NTRS2015

On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

Siles Perez, Jose Vicente↗
NASA NTRS1981

Investigation of semiconductor clad optical waveguides

The properties of semiconductor-clad optical waveguides based on glass substrates were investigated. Computer modeling studies on four-layer silicon-clad planar dielectric waveguides indicated that the attenuation and mode index should behave as exponentially damped sinusoids as the silicon thickness is decreased below one micrometer. This effect can be explained as a periodic coupling between the guided modes of the lossless structure and the lossy modes supported by the high refractive index silicon. The computer studies also show that both the attenuation and mode index of the propagating mode are significantly altered by conductivity charges in the silicon. Silicon claddings were RF sputtered onto AgNO3-NaNO3 ion exchanged waveguides and preliminary measurements of attenuation were made. An expression was developed which predicts the attenuation of the silicon clad waveguide from the attenuation and phase characteristics of a silicon waveguide. Several applications of these clad waveguides are suggested and methods for increasing the photo response of the RF sputtered silicon films are described.

Batchman, T. E.↗
NASA NTRS1993

Ballistic-Electron-Emission Microscopy Techniques for Nanometer-scale Characterization of Interfaces

Semiconductor interface properties are among the most important phenomena in materials science and technology. The study of metal/semiconductor Schottky barrier interfaces has been the primary focus of a large research and development community for decades. Throughout the long history of interface investigation, the study of interface defect electronic properties have been seriously hindered by the fundamental experimental difficulty of probing subsurface structures. A new method, Ballistic-Electron-Emission Microscopy (BEEM), has been developed which not only enables spectroscopic probing of subsurface interface properties, but also, provides nanometer-resolution imaging capabilities. BEEM employs Scanning Tunneling Microscopy (STM) and a unique spatially localized ballistic electron spectroscopy method...

Bell, L. D.↗