Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “PROCESSOR”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS2020

NEPP Processor Enclave: Testing Artificial Intelligence & Machine Learning

Computational device families are converging and multiple EEE components are required for a complete HPC subsystem. The components of this “processor enclave” are sensitive to radiation effects and therefore must be characterized for mission assurance. NEPP’s standardized approach to testing the Processor Enclave includes math, graphics, and AI and Machine Learning test vectors and device hardware capable of these applications.

Radiation testing↗
NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗
NASA NTRSDate not supplied

TechEdSat-13: The First Flight of an AI/ML Neuromorphic Processor

Neuromorphic processors, inspired by the wiring of the brain, permit certain classes of Artificial Intelligence/Machine Learning (AI/ML) algorithms to run far more efficiently. Ultimately, such systems will make the small- and nano-satellite platforms even more useful in terms of greatly improved power, communication and internal data management. In addition, on-board processing of images and data will help to not only rapidly interpret the information, but also reduce the amount of data that needs to be transmitted to ground stations. This initial flight experiment uses the Intel/ Loihi processor combined with a custom interface board and three communication channels to run the AI/ML scripts. These will vary with increasing length and complexity during the course of the mission. The algorithms will use the (at first) limited sensor data to ‘learn’ - with comparisons to similar architecture in comparable ground experiments. Some of the applications for successor flights in the TES-n flight series include Cognitive Communications, whereby the overall communication system is optimized per overflight – by optimizing timing and data transmission functions. Lastly, the performance of the Loihi 14nm process technology will be monitored for performance in the LEO radiation environment, thus looking for induced hardware and software errors. This information will help guide future radiation protection techniques to extend the lifetime and overall utility. The TES-13 is a 3U nanosat successfully launched by the Virgin Orbit Launcher-1 on January 13, 2022, and will presage more flights and AI/ML applications to come.

TechEdSat↗
NASA NTRS2022

TechEdSat-13: The First Flight of a Neuromorphic Processor

Neuromorphic processors, inspired by the wiring of the brain, permit certain classes of Artificial Intelligence/Machine Learning (AI/ML) algorithms to run far more efficiently. Ultimately, such systems will make the small- and nano-satellite platforms even more useful in terms of greatly improved power, communication and internal data management. In addition, on-board processing of images and data will help to not only rapidly interpret the information, but also reduce the amount of data that needs to be transmitted to ground stations. This initial flight experiment uses the Intel/Loihi processor combined with a custom interface board and three communication channels to run the AI/ML scripts. These will vary with increasing length and complexity during the course of the mission. The algorithms will use the (at first) limited sensor data to ‘learn’ - with comparisons to similar architecture in comparable ground experiments. Some of the applications for successor flights in the TES-n flight series include Cognitive Communications, whereby the overall communication system is optimized per overflight – by optimizing timing and data transmission functions. Lastly, the performance of the Loihi 14nm process technology will be monitored for performance in the LEO radiation environment, thus looking for induced hardware and software errors. This information will help guide future radiation protection techniques to extend the lifetime and overall utility. The TES-13 is a 3U nanosat successfully launched by the Virgin Orbit Launcher-1 on January 13, 2022, and will presage more flights and AI/ML applications to come.

TechEdSat↗
DOE OSTI2020

Mixed core processor unit

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗
DOE OSTI2022

High speed two-dimensional event detection and imaging using an analog interface and a massively parallel processor

A quantitative pulse count (event detection) algorithm with linearity to high count rates is accomplished by combining a high-speed, high frame rate camera with simple logic code run on a massively parallel processor such as a GPU or a FPGA. The parallel processor elements examine frames from the camera pixel by pixel to find and tag events or count pulses. The tagged events are combined to form a combined quantitative event image.

Waugh, Justin↗
DOE OSTI2016

A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm –2 s –1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. In conclusion, a thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Small-world complex network generation on a digital quantum processor

Abstract Quantum cellular automata (QCA) evolve qubits in a quantum circuit depending only on the states of their neighborhoods and model how rich physical complexity can emerge from a simple set of underlying dynamical rules. The inability of classical computers to simulate large quantum systems hinders the elucidation of quantum cellular automata, but quantum computers offer an ideal simulation platform. Here, we experimentally realize QCA on a digital quantum processor, simulating a one-dimensional Goldilocks rule on chains of up to 23 superconducting qubits. We calculate calibrated and error-mitigated population dynamics and complex network measures, which indicate the formation of small-world mutual information networks. These networks decohere at fixed circuit depth independent of system size, the largest of which corresponding to 1,056 two-qubit gates. Such computations may enable the employment of QCA in applications like the simulation of strongly-correlated matter or beyond-classical computational demonstrations.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Characterization of Quantum Frequency Processors

Frequency-bin qubits possess unique synergies with wavelength-multiplexed lightwave communications, suggesting valuable opportunities for quantum networking with the existing fiber-optic infrastructure. Although the coherent manipulation of frequency-bin states requires highly controllable multi-spectral-mode interference, the quantum frequency processor (QFP) provides a scalable path for gate synthesis leveraging standard telecom components. Here, we summarize the state of the art in experimental QFP characterization. Distinguishing between physically motivated “open box” approaches that treat the QFP as a multiport interferometer, and “black box” approaches that view the QFP as a general quantum operation, we highlight the assumptions and results of multiple techniques, including quantum process tomography of a tunable beamsplitter—to our knowledge the first full process tomography of any frequency-bin operation. Our findings should inform future characterization efforts as the QFP increasingly moves beyond proof-of-principle tabletop demonstrations toward integrated devices and deployed quantum networking experiments.

42 ENGINEERING↗
NASA NTRS2002

Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh, a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers, a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.

management locality load balance↗