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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 433 records · Page 24

Time-Shifted Boundary Conditions Used for Navier-Stokes Aeroelastic Solver

Under the Advanced Subsonic Technology (AST) Program, an aeroelastic analysis code (TURBO-AE) based on Navier-Stokes equations is currently under development at NASA Lewis Research Center s Machine Dynamics Branch. For a blade row, aeroelastic instability can occur in any of the possible interblade phase angles (IBPA s). Analyzing small IBPA s is very computationally expensive because a large number of blade passages must be simulated. To reduce the computational cost of these analyses, we used time shifted, or phase-lagged, boundary conditions in the TURBO-AE code. These conditions can be used to reduce the computational domain to a single blade passage by requiring the boundary conditions across the passage to be lagged depending on the IBPA being analyzed. The time-shifted boundary conditions currently implemented are based on the direct-store method. This method requires large amounts of data to be stored over a period of the oscillation cycle. On CRAY computers this is not a major problem because solid-state devices can be used for fast input and output to read and write the data onto a disk instead of storing it in core memory.

Srivastava, Rakesh↗

On-board Science Understanding: NASA Ames' Efforts

In the near future NASA intends to explore various regions of our solar system using robotic devices such as rovers, spacecraft, airplanes, and/or balloons. Such platforms will likely carry imaging devices, and a variety of analytical instruments intended to evaluate the chemical and mineralogical nature of the environment(s) that they encounter. Historically, mission operations have involved: (1) return of scientific data from the craft; (2) evaluation of the data by space scientists; (3) recommendations of the scientists regarding future mission activity; (4) commands for achieving these activities being transmitted to the craft; and (5) the activity being undertaken. This cycle is then repeated for the duration of the mission with command opportunities once or perhaps twice per day. In a rapidly changing environment, such as might be encountered by a rover traversing hundreds of meters a day or a spacecraft encountering an asteroid, this historical cycle is not amenable to rapid long range traverses, discovery of novelty, or rapid response to any unexpected situations. In addition to real-time response issues, the nature of imaging and/or spectroscopic devices are such that tremendous data volumes can be acquired, for example during a traverse. However, such data volumes can rapidly exceed on-board memory capabilities prior to the ability to transmit it to Earth. Additionally, the necessary communication band-widths are restrictive enough so that only a small portion of these data can actually be returned to Earth. Such scenarios clearly require the enabling of some crucial decisions to be made on-board by these robotic explorers. These decisions transcend the electromechanical control, health, and navigation issues associated with robotic operations. Instead they focus upon a long term goal of automating scientific discovery based upon data returned by sensors of the robot craft. Such an approach would eventually enable it to understand what is interesting because the data deviates from expectations generated by current theories/models of planetary processes that could have resulted in the observed data. Such interesting data and/or conclusions can then be selectively transmitted to Earth thus reducing memory and communications demands.

Roush, Ted L.↗

Image Compression Devices

The Rice algorithm is a "lossless" compression algorithm; it takes an image or other data that has been broken down into short strings of digital data, then processes each string mathematically to reduce the amount of memory required to store or transmit them. It is particularly useful in medical, scientific or engineering applications where all data must be preserved. Originally developed at Jet Propulsion Laboratory, the technology is marketed by Advanced Hardware Architectures, a company started by a former employee of the NASA Microelectronics Research Center.

Source record↗

Test-vehicle cycle programmer

Instrument reduces manpower needed for testing electric powered vehicles. Device has dual scale that allows operator to compare actual speed with preprogrammed test speed. Features include large meter, buzzer, packaging to allow ready interchange of memories with different profiles, small size, minimal current drain, and reverse supply voltage protection.

Lesco, D. J.↗

Programmable synaptic devices for electronic neural nets

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

Moopenn, A.↗

Performance of a Smart Vibration Isolator for Precision Spacecraft Instruments

Under the ARPA SMS Partnership Program for Synthesis and Processing of Smart Materials, Lockheed Missiles and Space company, Inc. has developed a demonstration prototype vibration cancelling mount using electrostrictive ceramic and shape-memory alloy actuators. Shape-memory actuators provide an adaptive-passive, self-damping support for isolation, while the electrostrictive actuators are employed to provide force and position control. The demonstration device was designed to address generic requirements for vibration stabilization of precision spacecraft instruments. It is reconfigurable to operate in any of four modes; passive isolation, active-passive isolation using force cancellation, active precision positioning, and active disturbance rejection. The presentation summarizes design of the device design and results of experimental evaluations of the device in isolation (active and passive) and positioning modes. Rejection of payload-borne disturbances is also discussed with reference to predictions from experimentally calibrated simulations. Finally, avenues for further development and refinement of the device are discussed.

Regelbrugge, Marc E.↗

Real Sky Performance of the Prototype sted Advanced Stellar Compass

The Danish microsatellite, sted, is equipped with an autonomous, advanced stellar compass (ASC). The ASC consists of two separate units, a Charge Coupled Device (CCD) camera head (based on a commercial Sony interline CCD detector) and a data processing unit with a powerful microcomputer (Intel 80486 type processor). The microcomputer memory contains a star catalogue which enables the microcomputer to recognize the constellations of stars in the field of vies and thus derive the attitude of the ASC camera head. The mission, and the design, operation and performance of the ASC are described. Results of the ASC prototype tests at the Jet Propulsion Laboratory (JPL) Table Mountain Observatory (TMO) facility are given.

orstedautonomous advanced stellar compass ASC adva↗

Design, processing, and testing of LSI arrays for space station

The development of a low power, high performance MOS 256-bit random assess memory with beam leads is discussed. Beam lead process development on silicon-on-sapphire (SOS) is also discussed, and initial electrical results on beam lead SOS TA5388 devices are presented. A comparison of the beam leaded 256-bit RAM (TA6567) layout is made with the non-beam leaded version (TA6473).

Schneider, W. C.↗

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Optical backplane interconnect switch for data processors and computers

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Hendricks, Herbert D.↗

A report of work activities on the NASA Spacelink public electronic library

NASA Spacelink is a comprehensive electronic data base of NASA and other source educational and informational materials. This service originates at Marshall Space Flight Center (MSFC) in Huntsville, Alabama. This is an education service of NASA Headquarters, through the MSFC Education Office, that first began in February of 1988. The new NASA Spacelink Public Electronic Library was the result of a study conducted to investigate an upgrade or redesign of the original NASA Spacelink. The UNIX Operating System was chosen to be the host operating system for the new NASA Spacelink Public Electronic Library. The UNIX system was selected for this project because of the strengths built into the embedded communication system and for its simple and direct file handling capabilities. The host hardware of the new system is a Sun Microsystems SPARCserver 1000 computer system. The configuration has four 50-MHz SuperSPARC processors with 128 megabytes of shared memory; three SB800 serial ports allowing 24 cable links for phone communications; 4.1 gigabytes of on-line disk storage; and ten (10) CD-ROM drives. Communications devices on the system are sufficient to support the expected number of users through the Internet, the local dial services, long distance dial services; the MSFC PABX, and the NPSS (NASA Packet Switching System) and 1-800 access service for the registered teachers.

Smith, Willard A.↗

An advanced programmable/reconfigurable color graphics display system for crew station technology research

The hardware configuration, software organization, and applications software for the NASA IKONAS color graphics display system are described. The systems were created at the Langley Research Center Display Device Laboratory to develop, evaluate, and demonstrate advanced generic concepts, technology, and systems integration techniques for electronic crew station systems of future civil aircraft. A minicomputer with 64K core memory acts as a host for a raster scan graphics display generator. The architectures of the hardware system and the graphics display system are provided. The applications software features a FORTRAN-based model of an aircraft, a display system, and the utility program for real-time communications. The model accepts inputs from a two-dimensional joystick and outputs a set of aircraft states. Ongoing and planned work for image segmentation/generation, specialized graphics procedures, and higher level language user interface are discussed.

Montoya, R. J.↗

Towards a Qualification Data Set: Expanded SEE Data on the P2020 Processor

Earlier P2020 SEE data are compared and expanded to a recent die revision, significantly increasing samples tested by protons by five devices, and by heavy ions by five devices. Earlier tested SEE types are found to be fairly similar in register, L1 cache, L2 cache, and CPU crashes. New test methods give SEE performance for the flash memory controller, watchdog circuit, and a built-in Ethernet port on the P2020 processor. Results from heavy ion and proton tests are presented, with data separated over a large number of specific error types and test programs.

Vartanian, Sargeh↗

Digital video image system

Interactive recording and display device acts as very-high-speed data-input/output interface between analog (video) signals and standard digital-computer components. System can be used with various picture and memory sizes and can be controlled manually or by computer.

Neely, P. L.↗

Sonoluminescence Bubble Measurements using Vision-Based Algorithms

Vision-based measurement methods were used to measure bubble sizes in this sonoluminescence experiment. Bubble imaging was accomplished by placing the bubble between a bright light source and a microscope-CCD camera system. A collimated light-emitting diode was operated in a pulsed model with an adjustable time delay with respect to the piezo-electric transducer drive signal. The light-emitting diode produced a bubble shadowgraph consisting of a multiple exposure made by numerous light pulses imaged onto a charge-couple device camera. Each image was transferred from the camera to a computer-controlled machine vision system via a frame grabber. The frame grabber was equipped with on-board memory to accomodate sequential image buffering while images were transferred to the host processor and analyzed. This configuration allowed the host computer to perform diameter measurements, centroid position measurements and shape estimation in "real-time" as the next image was being acquired. Bubble size measurement accuracy with an uncertainty of 3 microns was achieved using standard lenses and machine vision algorithms. Bubble centroid position accuracy was also within the 3 micron tolerance of the vision system. This uncertainty estimation accounted for the optical spatial resolution, digitization errors and the edge detection algorithm accuracy. The vision algorithms include camera calibration, thresholding, edge detection, edge position determination, distance between two edges computations and centroid position computations.

Hall, Nancy R.↗