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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

A simple second-order digital phase-locked loop.

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

Tegnelia, C. R.↗
NASA NTRS1973

An approach to the analysis of performance of quasi-optimum digital phase-locked loops.

An approach to the analysis of performance of quasi-optimum digital phase-locked loops (DPLL's) is presented. An expression for the characteristic function of the prior error in the state estimate is derived, and from this expression an infinite dimensional equation for the prior error variance is obtained. The prior error-variance equation is a function of the communication system model and the DPLL gain and is independent of the method used to derive the DPLL gain. Two approximations are discussed for reducing the prior error-variance equation to finite dimension. The effectiveness of one approximation in analyzing DPLL performance is studied.

Polk, D. R.↗
NASA NTRS1973

A Computer Model of a Phase Lock Loop

A computer model is reported of a PLL (phase-lock loop), preceded by a bandpass filter, which is valid when the bandwidth of the bandpass filter is of the same order of magnitude as the natural frequency of the PLL. New results for the PLL natural frequency equal to the bandpass filter bandwidth are presented for a second order PLL operating with carrier plus noise as the input. However, it is shown that extensions to higher order loops, and to the case of a modulated carrier are straightforward. The new results presented give the cycle skipping rate of the PLL as a function of the input carrier to noise ratio when the PLL natural frequency is equal to the bandpass filter bandwidth. Preliminary results showing the variation of the output noise power and cycle skipping rates of the PLL as a function of the loop damping ratio for the PLL natural frequency equal to the bandpass filter bandwidth are also included.

Shelton, Ralph Paul↗
NASA NTRS1973

Digital second-order phase-locked loop

A digital second-order phase-locked loop is disclosed in which a counter driven by a stable clock pulse source is used to generate a reference waveform of the same frequency as an incoming waveform, and to sample the incoming waveform at zero-crossover points. The samples are converted to digital form and accumulated over M cycles, reversing the sign of every second sample. After every M cycles, the accumulated value of samples is hard limited to a value SGN = + or - 1 and multiplied by a value delta sub 1 equal to a number of n sub 1 of fractions of a cycle. An error signal is used to advance or retard the counter according to the sign of the sum by an amount equal to the sum.

Holes, J. K.↗
NASA NTRS1974

A second-order all-digital phase-locked loop

A simple second-order digital phase-locked loop has been designed to synchronize itself to a square-wave subcarrier. Analysis and experimental performance are given for both acquisition behavior and steady-state phase error performance. In addition, the damping factor and the noise bandwidth are derived analytically. Although all the data are given for the square-wave subcarrier case, the results are applicable to arbitrary subcarriers that are odd symmetric about their transition region.

Holmes, J. K.↗
NASA NTRS1974

Quantizing and sampling considerations in digital phased-locked loops

The quantizer problem is first considered. The conditions under which the uniform white sequence model for the quantizer error is valid are established independent of the sampling rate. An equivalent spectral density is defined for the quantizer error resulting in an effective SNR value. This effective SNR may be used to determine quantized performance from infinitely fine quantized results. Attention is given to sampling rate considerations. Sampling rate characteristics of the digital phase-locked loop (DPLL) structure are investigated for the infinitely fine quantized system. The predicted phase error variance equation is examined as a function of the sampling rate. Simulation results are presented and a method is described which enables the minimum required sampling rate to be determined from the predicted phase error variance equations.

Hurst, G. T.↗
NASA NTRS1974

Response of an all digital phase-locked loop

An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.

Garodnick, J.↗
NASA NTRS1974

Phase-locked servo system

A phase lock servo system is described for synchronizing the rotation of a slip ring assembly with the rotation of an air bearing table so that a minimum of torque will be imparted through cables extending from the slip ring assembly to the air bearing table as such is rotated. The system includes two servo loops. The first servo loop includes a rate gyroscope carried on the air bearing table which generates a signal through a summing junction to be compared with a signal coming from a tachometer coupled to the slip ring assembly. The corrective signal is applied to a torque motor for rotating the slip ring assembly. The second servo loop includes a pair of photo detector cells which generate pulses responsive to the rotation of the air bearing table and slip ring assembly which are fed through a phase detector, and a variable gain amplifier to the summing junction circuit to provide a fine adjustment for rotating the slip ring assembly.

Burdin, C.↗
NASA NTRS1975

Digital phase-locked-loop speed sensor for accuracy improvement in analog speed controls

A digital speed control that can be combined with a proportional analog controller is described. The stability and transient response of the analog controller were retained and combined with the long-term accuracy of a crystal-controlled integral controller. A relatively simple circuit was developed by using phase-locked-loop techniques and total error storage. The integral digital controller will maintain speed control accuracy equal to that of the crystal reference oscillator.

Birchenough, A. G.↗
NASA NTRS1975

Digital phase-locked loop

An digital phase-locked loop is provided for deriving a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector.

Cliff, R. A.↗
NASA NTRS1975

Uniform sampling analysis of a hybrid phase-locked loop with a sample-and-hold phase detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.

Barab, S.↗
NASA NTRS1974

Binary phase lock loops for simplified OMEGA receivers

A sampled binary phase lock loop is proposed for periodically correcting OMEGA receiver internal clocks. The circuit is particularly simple to implement and provides a means of generating long range 3.4 KHz difference frequency lanes from simultaneous pair measurements.

Burhans, R. W.↗
NASA NTRS1975

Flow visualization of vortices locked by spanwise blowing over wings featuring a unique leading and trailing-edge flap system

Flow visualization studies were conducted to qualitatively determine the effects of active generation and augmentation of vortex flow over wings by blowing a discrete jet in a spanwise direction in the channel formed by extension of upper surface leading- and trailing-edge flaps. Spanwise blowing from a reflection plane over a rectangular wing was found to generate and lock a dual corotating vortex system within the channel and, at sufficient blowing rates, cause the separated flow off the upper end of the leading-edge flap to reattach to the trailing-edge flap. Test parameters included wing angle of attack, jet momentum coefficient, leading- and trailing-edge flap deflection angle, and jet location above the wing surface. Effects due to removal of the leading- and trailing-edge flap were also investigated.

Erickson, G. E.↗
NASA NTRS1976

Locking mechanism for orthopedic braces

A locking mechanism for orthopedic braces is described which automatically prevents or permits the relative pivotable movement between a lower brace member and an upper brace member. The upper and lower brace members are provided with drilled bores within which a slidable pin is disposed, and depending upon the inclination of the brace members with respect to a vertical plane, the slidable pin will be interposed between both brace members. The secondary or auxiliary latching device includes a spring biased, manually operable lever bar arrangement which is manually unlatched and automatically latched under the influence of the spring.

I-Lechao, J.↗
NASA NTRS1977

Extrasensitive phase-locked-loop circuit

Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.

Nyiri, E. J.↗
NASA NTRS1976

Command detector SNR estimator and lock status monitor circuitry

A breadboard of the command detector signal-to-noise-ratio estimator and lock status monitor was built on a wire-wrap card. The breadboard was integrated with the standard command detector, and its performance was measured. The design, design constraints, and construction of the breadboard are described. The performance is shown to agree with the theoretical model.

Emerson, R. F.↗