Photomultiplier gate for stimulated-spontaneous light scattering discrimination.
Photomultiplier gate for stimulated spontaneous light scattering discrimination, showing high cut- off efficiency, linearity and absence of spurious effect
CUT-OFF↗
SEARCH · Engineering Papers
Results for “GaTe”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Regulation of cyclic nucleotide-gated channels and membrane excitability in olfactory receptor cells by carbon monoxide
1. The effect of the putative neural messenger carbon monoxide (CO) and the role of the cGMP second-messenger system for olfactory signal generation was examined in isolated olfactory receptor neurons (ORNs) of the tiger salamander. 2. With the use of whole cell voltage-clamp recordings in combination with a series of ionic and pharmological tests, it is demonstrated that exogenously applied CO is a potent activator (K1/2 = 2.9 microM) of cyclic nucleotide-gated (CNG) channels previously described to mediate odor transduction. 3. Several lines of evidence suggest that CO mediates its effect through stimulation of a soluble guanylyl cyclase (sGC) leading to formation of the second-messenger cGMP. This conclusion is based on the findings that CO responses show an absolute requirement for guanosine 5'-triphosphate (GTP) in the internal solution, that no direct effect of CO on CNG currents in the absence of GTP is detectable, and that a blocker of sGC activation, LY85383 (10 microM), completely inhibits the CO response. 4. The dose-response curve for cGMP at CNG channels is used as a calibration to provide a quantitative estimate of the CO-stimulated cGMP formation. This analysis implies that CO is a potent activator of olfactory sGC. 5. Perforated patch recordings using amphotericin B demonstrate that low micromolar doses of CO effectively depolarize the membrane potential of ORNs through tonic activation of CNG channels. This effect in turn regulates excitable and adaptive properties of ORNs and modulates neuronal responsiveness. 6. These data argue for an important role of the cGMP pathway in olfactory signaling and support the idea that CO may function as a diffusible messenger in the olfactory system.
NASA Discipline Neuroscience↗
Ion Induced Electric Field Transients - The Single-Event Gate Rupture (SEGR)
Power MOSFET devices are susceptible to heavy-ion induced Single-Event Gate Rupture. Computer modeling show that intense electric field transients can trigger the SEGR phenomenon.
The Single-Event Gate Rupture (SEGR) Ion Induced E↗
Breakdown of Gate Oxides During Irradiation With Breakdown of Heavy Ions
Breakdown of gate oxides from heavy ions is investigated.
Ions Gate OxidesIrradiation Breakdown effects DRAM↗
Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics
In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.
adaptive hardwares↗
Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application
This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.
Mil Standard 883↗
Single Event Effects Test Results for Advanced Field Programmable Gate Arrays
Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.
Field Programmable Gate Arrays↗
TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays
We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.
protocol processing hardware engine↗
Re-Verification of the IRHN57133SE and IRHN57250SE for Single Event Gate Rupture and Single Event Burnout
The vertical metal oxide semiconductor field-effect transistor (MOSFET) is a widely used power transistor onboard a spacecraft. The MOSFET is typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single event gate rupture (SEGR) or single event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. These radiation hardened devices are not immune to SEGR or SEB but, rather, can exhibit them at a much more damaging ion than their non-radiation hardened counterparts. See [1] through [5] for more information.This effort was to investigate the SEGR and SEB responses of two power MOSFETs from IR(the IRHN57133SE and the IRHN57250SE) that have recently been produced on a new fabrication line. These tests will serve as a limited verification of these parts, but it is acknowledged that further testing on the respective parts may be needed for some mission profiles.
Single Event Gate Rupture (SEGR)↗
Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).
Xilinx Single-Event Effects (SEE) Test Consortium↗
Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices
An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.
Single Event Upset Testing↗
The NASA Electronic Parts and Packaging (NEPP) Program - Field Programmable Gate Array (FPGA) Tasks/Considerations
This presentation includes NASA Electronic Parts and Packaging (NEPP) Program Field Programmable Gate Array (FPGA) considerations and FPGA radiation tasks overview.
emerging commercial technologies↗
Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range
Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.
Transistor Gate Drive↗
NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing
This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.
Field Programmable Gate Array (FPGA); Triple Modul↗
Microsemi RTG4 Rev C Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report
The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of the Microsemi RTG4 device. The devices under test were the Microsemi RTG4 field programmable gate array (FPGA) Rev C. The devices under test will be referenced as the DUT or RTG4 Rev C throughout this document. The DUT was configured to have various test structures that are geared to measure specific potential susceptibilities of the device. DesignDevice susceptibility was determined by monitoring the DUT for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) was checked throughout heavy-ion testing by monitoring device current.
Field Programmable Gate Array (FPGA)↗
Radiation issues and applications of floating gate memories
The radiation effects that affect various systems that comprise floating gate memories are presented.
FAMOS↗
DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C
The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.
4H-SiC nJFET↗
DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C
The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.
4H-SiC nJFET↗