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Results for “Field programmable gate array”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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NASA Perspective on Microelectronic Components for Future Space Applications
No abstract available
G12 Task Group No. 2010-01 Class Y: a New QML Class for Non-Hermetic Space Products
No abstract available
Yearly Progress Update on the Class Y Initiative: Infusion of New Technology into the QML System
No abstract available
Wideband Spectroscopy: The Design and Implementation of a 3 GHz Bandwidth, 8192 Channel, Polyphase Digital Spectrometer
A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution unavailable elsewhere. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved Analog-to-Digital Converters, (ADC). This 6 Gsps (giga-sample per second) digital representation of the analog signal is then processed through an FPGA-based streaming Fast Fourier Transform (FFT), the key development described below. Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers. the implementation, results and underlying math for this spectrometer, as well as, potential for future extension to even higher bandwidth, resolution and channel orthogonality, needed to support proposed future advanced atmospheric science and radioastronomy, are discussed.
Wideband Spectroscopy: The Design and Implementation of a 3 GHz, 2048 Channel Digital Spectrometer
A state-of-the-art digital Fourier Transform spectrometer has been developed, with a combination of high bandwidth and fine resolution unavailable elsewhere. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved Analog-to-Digital Converters (ADC). This 6 Gsps (giga sample per second) digital representation of the analog signal is then processed through an FPGA-based streaming Fast Fourier Transform (FFT), the key development described below. Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers. The implementation, results and underlying math for this spectrometer, as well as potential for future extension to even higher bandwidth, resolution and channel orthogonality, needed to support proposed future advanced atmospheric science and radioastronomy, are discussed.
Software Defined GPS Receiver for the International Space Station
No abstract available
iFunction: Design and Implementation of a Programmable Function Generator IP Core for ISAAC Technology
No abstract available
SKA CSP Consortium : Capabilities and Interests of JPL
No abstract available
An FPGA-Based Back End for Real Time, Multi-Beam Transient Searches over a Wide Dispersion Measure Range
No abstract available
A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors
Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.
Single Event Effects in FPGA Devices 2014-2015
This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
Verification of Triple Modular Redundancy Insertion for Reliable and Trusted Systems
If a system is required to be protected using triple modular redundancy (TMR), improper insertion can jeopardize the reliability and security of the system. Due to the complexity of the verification process and the complexity of digital designs, there are currently no available techniques that can provide complete and reliable confirmation of TMR insertion. We propose a method for TMR insertion verification that satisfies the process for reliable and trusted systems.
Susceptibility of Redundant Versus Singular Clock Domains Implemented in SRAM-Based FPGA TMR Designs
We present the challenges that arise when using redundant clock domains due to their clock-skew. Radiation data show that a singular clock domain (DTMR) provides an improved TMR methodology for SRAM-based FPGAs over redundant clocks.
New Developments in Error Detection and Correction Strategies for Critical Applications
The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different FPGA device types.
Single Event Effects in FPGA Devices 2015-2016
This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
New Developments in Error Detection and Correction Strategies for Critical Applications
The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different FPGA device types.