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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

ECON-T and ECON-D: Endcap Concentrator ASICs for the CMS HGCAL

With over 6 million channels, the High Granularity Calorimeter (HGCAL) for the CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector data reduction for the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel). This presentation is the first comprehensive description of the ECON designs, first functionality and radiation tests for the ECON-T ASIC, and first results from the full production of 75k ECON-D and ECON-T ASICs.

Bergamin, G. [CERN] (ORCID:0000000285758704)↗
DOE OSTI2024

DS-GL: Advancing Graph Learning via Harnessing the Power of Nature within Dynamic Systems

With the rapid digitization of the world, an increasing number of real-world applications are turning to nonEuclidean data, modeled as graphs. Due to their intrinsic high complexity and irregularity, learning from graph data demands tremendous computational power. Recently, CMOS-compatible Ising machines, i.e., dynamic systems composed of CMOS components, have emerged as a new approach that harnesses the inherent power of natural annealing within dynamic systems to efficiently resolve binary optimization problems and have been adopted for traditional graph computation, such as max-cut. However, when performing complex Graph Learning (GL) tasks, Ising machines face significant hurdles: (i) they are inherently binary and thus ill-suited for real-valued problems; (ii) their expensive all-to-all coupling network that guarantees effective natural annealing poses daunting scalability concerns. To address these challenges, this paper proposes a nature-powered graph learning framework dubbed DS-GL, which is the first effort to transform the process of solving graph learning problems into the natural annealing process within a parameterized dynamic system embodied as a CMOS chip. To tackle the two major hurdles, DS-GL first augments the Ising machine architecture to modify the self-reaction term of its Hamiltonian function from linear to quadratic, effectively serving as an energy regulator. This adjustment maintains the system’s original physical interpretation while enabling it to process continuous, real-valued data. Second, to address the scaling issue, DS-GL further upgrades the real-valued dense Ising machine by decomposing it into a mesh-based multi-PE dynamic system that supports efficient distributed spatial-temporal co-annealing across different PEs through sparse interconnects. By exploiting the inherent sparsity and component structures in real-world graphs, DS-GL is able to map complex graph learning tasks onto the scalable dynamic system while maintaining high accuracy. Evaluations with three diverse GL applications across six real-world datasets, including traffic flow and COVID-19 prediction, show that DS-GL can deliver from 102× to 106× speedups and 500× energy reduction over Graph Neural Networks on GPUs, with 5% - 20% accuracy enhancement.

Song, Ruibing↗
DOE OSTI2026

Knowledge gaps for neuromorphic ionic computing

BACKGROUND Neuromorphic computing, inspired by the human brain’s ability to process information efficiently, represents a transformative approach to computation. In this Review, we explore the emerging field of neuromorphic ionic computing, which leverages ionic conduction and coupling to mimic neural processes, and identify critical knowledge gaps that must be addressed to realize its full potential. A central theme of the discussion is energy efficiency, a challenge that is both a limitation and an opportunity for this technology. Although complementary metal-oxide semiconductor (CMOS)–based neuromorphic technologies have made strides in scaling to billions of neurons and are increasingly applied in artificial intelligence and numerical computing, they remain orders of magnitude behind the human brain in terms of connectivity and energy efficiency. Neuromorphic ionic computing promises to overcome these limitations by leveraging the distinct architectural and operational principles of the brain. Our brains achieve this energy efficiency by combining several key features: using the same network elements to store and process information; using an incredibly complex and massively interconnected three-dimensional (3D) network of locally active elements that enables sparsity, robustness in the presence of noise, adaptation, and life-long learning; computing at comparatively low voltage and frequency; and last, taking advantage of a plethora of ions and small molecules as information carriers. Here, we propose that ionic computing systems can take advantage of similar features to achieve substantial gains in energy efficiency. ADVANCES Since the first reports of neuromorphic ionic behavior in nanofluidic channels, we have witnessed an explosion of reports that used ionic devices to produce synaptomimetic behaviors. However, achieving the goals of ionic computing requires not only implementation of much more sophisticated device functionality but also overcoming fundamental barriers in materials science, device architecture, and system integration. Current ionic devices, even those incorporating state-of-the-art materials, still suffer from limited functionality and stability, which restrict their performance and increase energy demands. Developing new materials with enhanced ionic properties is essential to overcome these limitations. Similarly, the design of neuromorphic devices must evolve to leverage the particular advantages of ionic processes. Existing architectures often follow a single-information-carrier logic of conventional electronics or are constructed of mesoscale fluidics, failing to capitalize on the energy-efficient mechanisms inherent to ionic systems or implement the multiple-information-carrier paradigm. Current neuromorphic chips focus on large-scale networks of analog memory elements based on mechanisms such as charge trap (flash), filamentary, phase change, or spin, which are built on top of a network of artificial CMOS neurons. Although such prototype networks have achieved impressive performance, it is difficult to envision how they can implement the key features such as massive connectivity, sophisticated plasticity, adaptability, sparsity, and “multichromatic” computing. Although small-scale devices have demonstrated promising results, integrating them, maintaining energy efficiency, and implementing temperature control as systems grow in complexity and size to computationally relevant scale remain major hurdles. Furthermore, interfacing neuromorphic ionic devices with existing computing technologies presents technical and conceptual challenges that will require innovative approaches that combine insights from neuroscience, materials science, and engineering. OUTLOOK Despite these challenges, the potential impact of neuromorphic ionic computing is profound with potential applications ranging from artificial intelligence to robotics and beyond. We also argue that neuromorphic ionic computing systems should not, at least in the beginning, compete with CMOS technologies but rather should focus on applications that require extreme energy efficiency with chemical and/or biological compatibility, such as biomedical applications (for example, brain-computer interfaces), environmental monitoring, and agricultural and food applications. Ultimately, this Review highlights the crucial role of interdisciplinary collaboration in advancing the field. Neuromorphic ionic computing is not merely a technological innovation; it represents a substantial step toward sustainable computation, aligning with the growing demand for energy-conscious solutions in a world that is increasingly reliant on data and computation.

Neuromorphic↗
DOE OSTI2021

Silicon Nanosheets as Candidates for Silicon-Based Optoelectronics

The growth in computational ability over the past decades has positively impacted global development, the economy, healthcare, and science. As on-chip components are approaching the atomic scale, alternative paradigms are needed to address the thermal and electronic issues that impose bottlenecks for computing. One approach to address this is with optoelectronics. However, silicon—the backbone of microelectronics—is a poor choice due to its indirect bandgap, while existing optoelectronic materials are incompatible with CMOS infrastructure. Monolayer silicon nanosheets (SiNSs) are an intriguing material that exhibit photoluminescence, and are compositionally-compatible with the CMOS process. Here, we synthesize and characterize monolayer SiNSs, and show spectroscopic evidence that they exhibit a quasi-direct bandgap, which is corroborated by DFT calculations. We probe their thermal stability, demonstrating their structure and photoluminescence are stable beyond the required operating temperatures for computing applications. These optoelectronic properties, CMOS-compatibility, and stability make SiNSs a viable candidate for silicon-based photonics.

Ryan, Bradley↗
DOE OSTI2023

Milestone report for MRT 8479: High Yield Xray Imager Preliminary Design Review

The High Yield Xray Imager (HYXI) is a new NIF target diagnostic system currently under development. The goal of HYXI is to provide high-fidelity, high temporal resolution x-ray imaging capability on high yield NIF implosions at 10MJ and above. The HYXI instrument design concept is based on the combination of two technologies that have been successfully utilized at the NIF on previous instruments, electron pulse-dilation and hybrid-CMOS sensor imaging. The combination of these two techniques will give HYXI sufficient data quality to ascertain differences in hot spot formation dynamics between high and low yield implosions. This information will highlight the critical hot spot conditions needed for ignition and burn. The HYXI design leverages the successful operation of the PDIXI x-ray imager at the NIF on multi-MJ yield shots. Also, a new radiation tolerance CMOS imaging array is being developed to eliminate the significant background noise which limits the data quality of PDIXI. The HYXI Preliminary Design Review was completed at the end of Q4 FY23. The HYXI project is a multi-year effort with a phased approach to be bring up system functionality over time in parallel with the development and fabrication effort of the new CMOS imaging array. Initial time integrated NIF data will be collected in Q2 FY25, first time resolved imaging with Daedalus starting in Q2 FY26 and the final performance qualification of the complete HYXI system is scheduled for Q2 FY27.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

High Yield Xray Imager Final Design Review

The High Yield Xray Imager (HYXI) is a new NIF target diagnostic system currently under development. The goal of HYXI is to provide high-fidelity, high temporal resolution x-ray imaging capability on high yield NIF implosions at 10MJ and above. The HYXI instrument design concept is based on the combination of two technologies that have been successfully utilized at the NIF on previous instruments, electron pulse-dilation and hybrid-CMOS sensor imaging. The combination of these two techniques will give HYXI sufficient data quality to ascertain differences in hot spot formation dynamics between high and low yield implosions. This information will highlight the critical hot spot conditions needed for ignition and burn. The HYXI design leverages the successful operation of the PDIXI x-ray imager at the NIF on multi MJ yield shots. A new radiation tolerant CMOS imaging array (HYPERION) is being developed to eliminate the significant background noise which limits the data quality of PDIXI. We successfully placed the contract with Advanced hCMOS Systems (AHS) to develop the HYPERION sensor, which fulfils our criteria to place long lead time item procurements by end of FY24. The HYXI Final Design Review was completed at the end of Q4 FY24 (Sep 24 th and Sep 30 th ). The HYXI project is a multi-year effort with a phased approach to be bring up system functionality over time in parallel with the development and fabrication effort of the HYPERION CMOS imaging array. In Phase 1, time-integrated x-ray images on NIF DT experiments will be collected starting in Q3 FY25. In Phase 2 of the project, time-resolved imaging with HYXI utilizing a spare microchannel plate detector back-end will begin in Q3 FY26. Phase 3 concludes the project with the installation of the HYPERION sensor array and the final performance qualification of the HYXI instrument which is scheduled for Q3 FY27 as discussed in the PDR and MRT report on this project in FY23.

42 ENGINEERING↗
DOE OSTI2023

Wireless System Development for GaN-Based Transmitters for Advanced Nuclear Reactor Environments

The market for consumer electronics is dominated by Si-based electronics. Many Si-based complementary metal–oxide–semiconductor (CMOS) devices are reaching their limitations in terms of switching frequencies, voltages, currents, and temperatures. Furthermore, these devices are widely known to be susceptible to ionizing radiation and neutrons. Advanced nuclear reactors, especially microreactors and small modular reactors, require wireless electronics that can survive larger neutron and gamma doses than Si CMOS. Because of their size, electronics will need to be placed closer to the reactor cores, and cabling capabilities may be limited. However, GaN high-electron-mobility transistors (HEMTs) have been shown to switch faster with higher gains, and they can achieve current and voltage limits beyond traditional Si CMOS. However, they have less market maturity and have undergone less testing. These GaN HEMTs have been shown to survive ionizing radiation with little effects, but the effects of neutron radiation remain widely unknown. In this report, a wireless electronic system capable of supporting multiple radiation-hardened (rad-hard) sensors is presented. The proposed transmission scheme was designed to be simple to increase the likelihood of success in the immature GaN HEMT process and in high-radiation environments. The transmission system was tested using software-defined radios to emulate the transmission scheme before the transmitter circuitry in the GaN process was developed.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

28nm front end ASIC and 12” LGADs for 3D integration

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (≈10 μm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present the design and results from a 28 nm CMOS ASIC prototype, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. We also report on the co-design and characterization of reticle-scale LGAD sensors with 50 μm and 100 μm pixels and introduce the next 10k-pixel ASIC designed for full 3D integration. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2024

Digital Miniature Cathode Ray Magnetometer

In this study, we introduce the concept and construction of an innovative Digital Miniature Cathode Ray Magnetometer designed for the precise detection of magnetic fields. This device addresses several limitations inherent to magnetic probes such as D.C. offset, nonlinearity, temperature drift, sensor aging, and the need for frequent recalibration, while capable of operating in a wide range of magnetic fields. The core principle of this device involves the utilization of a charged particle beam as the sensitivity medium. The system leverages the interaction of an electron beam with a scintillator material, which then emits visible light that is captured by an imager. The emitted scintillation light is captured by a CMOS sensor. This sensor not only records the scintillation light but also accurately determines the position of the electron beam, providing invaluable spatial information crucial for magnetic field mapping. The key innovation lies in the combination of electron beam projection, CMOS imager scintillation-based detection, and digital image signal processing. By employing this synergy, the magnetometer achieves remarkable accuracy, sensitivity and dynamic range. The precise position registration enabled by the CMOS sensor further enhances the device’s utility in capturing complex magnetic field patterns, allowing for 2D field mapping. In this work, the optimization of the probe’s performance is tailored for applications related to the characterization of insertion devices in light sources, including undulators.

Turqueti, Marcos↗
NASA NTRS1971

Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.

Feller, A.↗
NASA NTRS1977

The effects of the geosynchronous energetic particle radiation environment on spacecraft charging phenomena

The energetic electron environment at the geosynchronous orbit is responsible for a variety of adverse charging effects on spacecraft components. The most serious of these is the degradation and failure of a complementary-metal-oxide-semiconductor (CMOS) electronic components as a result of internal charge-buildup induced by the energetic electrons. Efforts to accurately determine the expected lifetime of these components in this orbit are hampered by the lack of detailed knowledge of the electron spectrum and intensity, particularly of the more penetrating energies greater than 1.5 MeV. This problem is illustrated through the calculation of the dose received by a CMOS device from the energetic electrons and associated bremsstrahlung as a function of aluminum shielding thickness using the NASA AE-6 and the Aerospace measured electron environments. Two computational codes which were found to be in good agreement were used to perform the calculations. For a given shielding thickness the dose received with the two radiation environments differ by as much as a factor of seven with a corresponding variation in lifetime of the CMOS.

Reagan, J. B.↗
NASA NTRS1977

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Stahl, R. H.↗
NASA NTRS1977

C-MOS bulk metal design handbook

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

Edge, T. M.↗
NASA NTRS1978

Design, development, fabrication and delivery of register and multiplexer units

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Feller, A.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS1986

Coating Circuit Boards With Silicone

Techniques appropriate to boards containing CMOS circuits detailed. Document presents procedure for applying thin conformal coating to such electronic assemblies as printed-circuit boards and wire-wrapped boards. Coating is from 1 to 7 mils (25 to 178 micrometers) thick and composed of room-temperature-vulcanizing (RTV) silicone. Specifies materials, equipment, spraying method, and quality requirements. Takes into account special needs of circuits made with complementary metal-oxide/semiconductor (CMOS) devices on circuit boards. Special attention given to preventing damage by electrostatic discharge, to which CMOS circuits especially sensitive.

Gaudiano, S.↗