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At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Lithium indium diselenide — An advanced material for neutron detection

Here, this paper describes the synthesis, crystal growth, detector fabrication, radiation hardening studies, MCNP modeling, and characterization of lithium indium diselenide or LiInSe 2 . This newly-developed room temperature thermal neutron detector has semiconducting and scintillating properties and it is suitable for neutron detection application. LiInSe 2 was synthesized starting from elemental Li, In, Se in two steps due to high reactivity of Li. A single crystal of LiInSe 2 was grown using the Vertical Bridgman method. The room temperature band gap was found to be 2.8 eV using optical absorption measurements. Bulk resistivity was measured at ∼5 × 10 11 Ωcm. Photoconductivity measurements of LiInSe 2 wafers identified a peak in the photocurrent around 445 nm. Nuclear radiation detectors were fabricated from single crystal wafer and the responses to alpha particles at various biases were measured. The mobility-lifetime product was estimated. Gamma irradiation studies were performed with calculated absorbed doses ranging from 0.2126 to 21,262 Gy. The characterization of the two wafers for their scintillator performance was conducted after each irradiation. The gamma irradiation produced a reduction of the light yield that translated to a lower channel number for the centroid of alpha detection spectra. It also showed a considerable reduction of the decay time after the first irradiation. These are the first studies on gamma radiation hardening with this material.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

PERC silicon PV infrared to ultraviolet optical model

Here, optical modeling of aluminum back surface field (Al-BSF) and passivated emitter and rear contact (PERC) silicon wafer solar cells are extended into the infrared wavelength range (300–2500 nm). The model incorporates ray tracing to account for pyramidal texture of the front silicon surface, free carrier absorption in the front emitter; bulk silicon wafer, BSF; and Lambertian scattering at the silicon back contact. Total reflectance of pyramidal textured cells with different contact geometries with and without encapsulation are simulated. Simulated reflectance and short circuit current density match well with experimental values. These physics-based optical models serve as input for evaluating optical and thermal management strategies for silicon wafer solar cells.

14 SOLAR ENERGY↗
DOE OSTI2023

Understanding the origin of Tabula Rasa-induced defects in n-type Cz c-Si: The case of nitrogen atmosphere

Phosphorus-doped Czochralski-grown silicon (Cz-Si) has been gaining market share in the large-scale manufacturing of high-efficiency silicon (Si)-based photovoltaic (PV) devices thanks to higher carrier lifetimes than their boron-doped counterpart. However, the fabrication of n-type Cz-Si based solar cells often requires process steps with much higher temperatures and longer times than p-type Silicon. Defect interaction with the high temperatures during such processes tend to be detrimental to the n-type Cz-Si carrier lifetime, therefore limiting the final device efficiency. Short thermal anneals before cell processing, known as Tabula Rasa (TR), have been proposed to mitigate the thermally induced lifetime degradation during n-type Cz-Si solar cell fabrication. This work thoroughly investigates the defects responsible for the lifetime degradation after TR in a N 2 atmosphere treatment. We use temperature-injection-dependent lifetime spectroscopy and the thickness variation method to decouple the effects of TR treatment in the bulk and the surface of the n-type Cz-Si wafers. Using the defect parameter contour mapping (DPCM), we identify the defect energy level (E t ) and the capture cross-section ratio (k) of the most likely process-induced defect, which aligns with previously proposed Si vacancy-associated defects. The DPCM reveals that these vacancy-associated defects have a shallow energy level E t - E v ~0.13 eV and very efficient electron capture cross section k~600. Unexpectedly, the bulk degradation due to vacancy defects in the volume of the wafer, is accompanied by a significant increase in the surface recombination as well. Through evaluating the surface recombination velocity temperature- and injection dependence, we show that after TR, at room temperature and for an injection level of 10 15 cm -3 , in a wafer passivated with a-Si:H(i) the surface recombination dominates the overall lifetime response. Here we hypothesize that the near surface vacancy-associated bulk defects play a role in lowering the electron diffusion current into the a-Si:H(i) from the c-Si(n) reducing the field-effect passivation.

14 SOLAR ENERGY↗
DOE OSTI2025

Resistivity distribution and donor properties of antimony-doped n -type Czochralski silicon ingots

We investigate antimony (Sb)-doped Czochralski-grown silicon as an alternative n-type substrate for photovoltaic applications, and characterize their axial resistivity distribution, donor properties, and mechanical strength. We find that Sb-doped ingots can achieve a more uniform resistivity distribution along the axial direction compared to P-doped counterparts. Dopant concentration profiles in P-doped ingots can be accurately modelled using the standard Scheil's equation, accounting only for dopant segregation during solidification. In contrast, modelling Sb-doped ingots requires consideration of both dopant segregation and evaporation effects to fit the dopant distribution accurately. Using electron paramagnetic resonance spectroscopy at 9 K, we observe two hyperfine lines in P-doped samples, and six hyperfine lines for Sb 121 and eight for Sb 123 isotopes, with the number of hyperfine lines governed by the nuclear spins. We further identify two-atom Sb clustering in the Sb-doped wafers, confirmed through simulations of the additional weak electron paramagnetic resonance peaks. Finally, we find that 140 μm as-cut planar Sb-doped wafers exhibit slightly higher mechanical strength compared to P-doped wafers.

14 SOLAR ENERGY↗
DOE OSTI2026

Development of a Flow-through Cell for Ultrasonic Extraction (UE)─Single Particle (SP)─ICP-MS─an Approach for Nano/Microparticle Elemental and Isotopic Analysis

Nanotechnology is a salient part of the scientific landscape, and analytical approaches are rapidly evolving to enable small-scale characterization of nano- and microparticle compositions and impurities. Here, a flow-through sonicating cell was developed for direct particle extraction from a silicon wafer and integrated with an inductively coupled plasma–mass spectrometer (ICP-MS) for subsequent elemental and isotopic characterization of the released particles. Ultrasonic extraction (UE)─single particle (SP)─ICP-MS offers controlled particle mobilization from solid substrates and allows for increased sample throughput by eliminating the need for pre-extraction of particles and decreasing sample preparation steps. Coupling this device to an ICP-MS with a time-of-flight (TOF) mass analyzer, it is possible to distinguish unique isotopic compositions of the particles. Both tungsten and nickel isotopically tagged particles, which were deposited on Si wafers, are presented here with analysis via UE─SP─ICP-MS. This approach could support efforts in the fields of particle synthesis, nuclear safeguards and forensics, environmental monitoring, and semiconductor industries in which the detection of particles from substrates and wafers is critical.

Paul, Molly [ORNL] (ORCID:0009000009672055)↗
DOE OSTI2020

Selective-Area Remote Epitaxy of ZnO Microrods Using Multilayer–Monolayer-Patterned Graphene for Transferable and Flexible Device Fabrications

Here, selective-area remote epitaxy (SA-REpi) is demonstrated for fabricating mechanically releasable position-controlled ZnO microrod (MR) arrays from donor wafers in an arrayed form. Intaglio-patterned graphene, consisting of basal single-layer graphene (SLG) overlayered with multilayer graphene (MLG) patterned with perforated holes, is transferred onto a GaN/Al 2 O 3 wafer on which the hydrothermal synthesis is performed for growing ZnO MRs. The basal SLG area exposed through the MLG pattern yields ZnO MRs, whereas the MLG plateau inhibits the growth. The noncovalent remote epitaxial heterointerface enables the release of the MR overlayer in the arrayed form, and the original source wafer is refurbished for reproducibly repeating the SA-REpi. Density-functional theory calculations suggest that localized surface charge density is induced on the surface of SLG by the underlying GaN across ultrathin SLG, which possibly provides a driving force for precursor adatoms and the following remote epitaxy of ZnO. In contrast, the induction of the charge density redistribution does not clearly occur through MLG; so, that keeps the surface of MLG nearly charge-neutral. The diameter and spacing of ZnO MRs are controlled in a designed way by changing the pattern geometries. High-resolution scanning transmission electron microscopy reveals the remote heteroepitaxial relationship at an atomic level. The remote epitaxy is expected to provide an ideal platform to transfer the addressable spatial arrays of nano- or micro-architecture semiconductor components to arbitrary target surfaces directly after the growth without the assembly procedures.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Voltage waveform tailoring for high aspect ratio plasma etching of SiO 2 using Ar/CF 4 /O 2 mixtures: Consequences of low fundamental frequency biases

The use of non-sinusoidal waveforms in low pressure capacitively coupled plasmas intended for microelectronics fabrication has the goal of customizing ion and electron energy and angular distributions to the wafer. One such non-sinusoidal waveform uses the sum of consecutive harmonics of a fundamental sinusoidal frequency, f 0 , having a variable phase offset between the fundamental and even harmonics. In this paper, we discuss results from a computational investigation of the relation between ion energy and DC self-bias when varying the fundamental frequency f 0 for capacitively coupled plasmas sustained in Ar/CF 4 /O 2 and how those trends translate to a high aspect ratio etching of trenches in SiO 2 . The fundamental frequency, f 0 , was varied from 1 to 10 MHz and the relative phase from 0° to 180°. Two distinct regimes were identified. Average ion energy onto the wafer is strongly correlated with the DC self-bias at high f 0 , with there being a maximum at φ = 0° and minimum at φ = 180°. In the low frequency regime, this correlation is weak. Average ion energy onto the wafer is instead dominated by dynamic transients in the applied voltage waveforms, with a maximum at φ = 180° and minimum at φ = 0°. The trends in ion energy translate to etch properties. In both, the high and low frequency regimes, higher ion energies translate to higher etch rates and generally preferable final features, though behaving differently with phase angle.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Development of “GaSb-on-silicon” metamorphic substrates for optoelectronic device growth

The epitaxial development and characterization of metamorphic “GaSb-on-silicon” buffers as substrates for antimonide devices is presented. The approach involves the growth of a spontaneously and fully relaxed GaSb metamorphic buffer in a primary epitaxial reactor, and use of the resulting “GaSb-on-silicon” wafer to grow subsequent layers in a secondary epitaxial reactor. The buffer growth involves four steps—silicon substrate preparation for oxide removal, nucleation of AlSb on silicon, growth of the GaSb buffer, and finally capping of the buffer to prevent oxidation. This approach on miscut silicon substrates leads to a buffer with negligible antiphase domain density. The growth of this buffer is based on inducing interfacial misfit dislocations between an AlSb nucleation layer and the underlying silicon substrate, which results in a fully relaxed GaSb buffer. A 1 μm thick GaSb layer buffer grown on silicon has ~9.2 × 10 7 dislocations/cm 2 . The complete lack of strain in the epitaxial structure allows subsequent growths to be accurately lattice matched, thus making the approach ideal for use as a substrate. Here we characterize the GaSb-on-silicon wafer using high-resolution x-ray diffraction and transmission electron microscopy. The concept’s feasibility is demonstrated by growing interband cascade light emitting devices on the GaSb-on-silicon wafer. The performance of the resulting LEDs on silicon approaches that of counterparts grown lattice matched on GaSb.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Ultra-low loss visible light waveguides for integrated atomic, molecular, and quantum photonics

Atomic, molecular and optical (AMO) visible light systems are the heart of precision applications including quantum, atomic clocks and precision metrology. As these systems scale in terms of number of lasers, wavelengths, and optical components, their reliability, space occupied, and power consumption will push the limits of using traditional laboratory-scale lasers and optics. Visible light photonic integration is critical to advancing AMO based sciences and applications, yet key performance aspects remain to be addressed, most notably waveguide losses and laser phase noise and stability. Additionally, a visible light integrated solution needs to be wafer-scale CMOS compatible and capable of supporting a wide array of photonic components. While the regime of ultra-low loss has been achieved at telecommunication wavelengths, progress at visible wavelengths has been limited. Here, we report the lowest waveguide losses and highest resonator Qs to date in the visible range, to the best of our knowledge. We report waveguide losses at wavelengths associated with strontium transitions in the 461 nm to 802 nm wavelength range, of 0.01 dB/cm to 0.09 dB/cm and associated intrinsic resonator Q of 60 Million to 9.5 Million, a decrease in loss by factors of 6x to 2x and increase in Q by factors of 10x to 1.5x over this visible wavelength range. Additionally, we measure an absorption limited loss and Q of 0.17 dB/m and 340 million at 674 nm. This level of performance is achieved in a wafer-scale foundry compatible Si 3 N 4 platform with a 20 nm thick core and TEOS-PECVD deposited upper cladding oxide, and enables waveguides for different wavelengths to be fabricated on the same wafer with mask-only changes per wavelength. These results represent a significant step forward in waveguide platforms that operate in the visible, opening up a wide range of integrated applications that utilize atoms, ions and molecules including sensing, navigation, metrology and clocks.

Chauhan, Nitesh↗
DOE OSTI2022

Silicon nitride stress-optic microresonator modulator for optical control applications

Modulation-based control and locking of lasers, filters and other photonic components is a ubiquitous function across many applications that span the visible to infrared (IR), including atomic, molecular and optical (AMO), quantum sciences, fiber communications, metrology, and microwave photonics. Today, modulators used to realize these control functions consist of high-power bulk-optic components for tuning, sideband modulation, and phase and frequency shifting, while providing low optical insertion loss and operation from DC to 10s of MHz. In order to reduce the size, weight and cost of these applications and improve their scalability and reliability, modulation control functions need to be implemented in a low loss, wafer-scale CMOS-compatible photonic integration platform. The silicon nitride integration platform has been successful at realizing extremely low waveguide losses across the visible to infrared and components including high performance lasers, filters, resonators, stabilization cavities, and optical frequency combs. Yet, progress towards implementing low loss, low power modulators in the silicon nitride platform, while maintaining wafer-scale process compatibility has been limited. Here we report a significant advance in integration of a piezo-electric (PZT, lead zirconate titanate) actuated micro-ring modulation in a fully-planar, wafer-scale silicon nitride platform, that maintains low optical loss (0.03 dB/cm in a 625 µm resonator) at 1550 nm, with an order of magnitude increase in bandwidth (DC - 15 MHz 3-dB and DC - 25 MHz 6-dB) and order of magnitude lower power consumption of 20 nW improvement over prior PZT modulators. The modulator provides a >14 dB extinction ratio (ER) and 7.1 million quality-factor (Q) over the entire 4 GHz tuning range, a tuning efficiency of 162 MHz/V, and delivers the linearity required for control applications with 65.1 dB·Hz 2/3 and 73.8 dB·Hz 2/3 third-order intermodulation distortion (IMD3) spurious free dynamic range (SFDR) at 1 MHz and 10 MHz respectively. We demonstrate two control applications, laser stabilization in a Pound-Drever Hall (PDH) lock loop, reducing laser frequency noise by 40 dB, and as a laser carrier tracking filter. This PZT modulator design can be extended to the visible in the ultra-low loss silicon nitride platform with minor waveguide design changes. This integration of PZT modulation in the ultra-low loss silicon nitride waveguide platform enables modulator control functions in a wide range of visible to IR applications such as atomic and molecular transition locking for cooling, trapping and probing, controllable optical frequency combs, low-power external cavity tunable lasers, quantum computers, sensors and communications, atomic clocks, and tunable ultra-low linewidth lasers and ultra-low phase noise microwave synthesizers.

Wang, Jiawei (ORCID:0000000257965220)↗
DOE OSTI2020

Rapid Patterning and Advanced Device Structures for Low Cost Manufacturable Crystalline Si IBC Cells

Recent record efficiency Si cells have had an interdigitated back contact (IBC) design where both positive and negative contacts are fabricated on the back side of the Si wafer. Many industry groups have investigated IBC cells but used photolithography to pattern the rear contacts although it is considered impractical for low cost, high volume manufacturing. Alternative patterning methods using lasers and mechanical masking have been utilized in fabrication of patterned regions in IBC Si solar cells to replace photolithography. Another exciting advance in Si solar cell technology has been replacing the high temperature diffusion of doped regions inside the crystalline Si wafer with low temperature deposition of very thin layers of doped amorphous hydrogenated Si (a-Si:H) on the Si wafer. This is called a Si heterojunction (HJ) device. The a-Si:H provides excellent passivation of surface defects and has produced the highest open circuit voltages (VOC) of any Si solar cell device structure. The Institute of Energy Conversion (IEC) demonstrated the first IBC-HJ solar cell combining these two strategies in 2007 and has fabricated IBC-HJ cells with 20% efficiency using three photolithography steps. Despite the demonstrated efficiency potential of this device by industry groups (>26%) there is no commercial production because of the challenges of patterning and processing the structure in an industrial environment. Our work sought to address that challenge. The objective of this 3 year project was to develop the processing for the IBC-HJ Si solar cell using lasers for patterning and contact formation instead of photolithography. Laser patterning enables rapid, contactless manufacturing of patterned regions. We intensively studied laser fired contacts, laser patterning of the a-Si multi-layer stacks and metal layers and the use of plasma shadow masks. After an exhaustive focus in the first year on the laser fired emitter (LFE) and contact (LFC), we were unable to achieve VOC greater than 660 mV, compared to the 720 mV required to meet our milestones. We discovered that an additional issue with our original IBC structure was the presence of an inversion layer at the back surface connecting the p and n regions which reduced the VOC and fill factor (FF). We developed innovative methods for characterizing the inversion layer. These two limitations in the original design lead to development of a new IBC-HJ process sequence and device structure which we called Plasma Masked Laser Processed (PMLP). It retained the original high efficiency features including manufacturability. The LFC was replaced with a standard n-type a-Si HJ contact. The inversion layer was eliminated by replacing the previous p-type stack in the gap with an n-type or SiN stack. The PMLP used laser ablation of a multi-layer a-Si stack followed by chemical etching to open the n-contact. It required deposition of a patterned stack through a mask in the plasma deposition chamber. This turned out to be a source of significant problems due to inevitable unwanted deposition ‘leakage’ under the mask. This formed a blocking contact on the emitter which significantly reduced Voc and FF. Several iterations in PMLP device structure and chemical etching steps resulted in a large improvements, e.g. the efficiency increasing from 3 to 15% and Voc from 450 to 660 mV but they were unable to completely eliminate it. The best IBC-HJ device we fabricated had only 15% efficiency. For perspective, our standard FHJ devices had 20% efficiency.

14 SOLAR ENERGY↗
DOE OSTI2020

Mixed-dimensional stackable electronics enabled by freestanding 2D/3D materials

2D material-based devices have received great deal of attention as they can be easily stacked to obtain multifunctionality. With their ultrathin thicknesses, such multifunctioning devices become so flexible and conformal that they can be placed onto any 3D featured surfaces. However, 2D heterostructures are typically demonstrated as stacked flakes where single or few devices can be fabricated due to lack of strategies for layer-by-layer stacking of 2D materials at the wafer scale. In this talk, I will discuss about our unique strategy to isolate wafer-scale 2D materials into monolayers and stack them into a heterostructures by using a layer-resolved splitting (LRS) technique. This technique enables my group at MIT to explore unprecedented wafer-scale 2D heterodevices including integrated photonics, 3D neuromorphic computing, and microLEDs, which will be introduced in my talk. While 2D heterostructures promise interesting futuristic devices, the performance of 2D material-based devices is substantially inferior to that of conventional 3D semiconductor materials. However, 3D materials exist as their bulk form, thus it is challenging to stack them together for heterostructures. Obviously, conformal coating of such single-crystalline bulks on 3D features is impossible. My group at MIT has recently invented a 2D materials-based layer transfer (2DLT) technique that can produce single-crystalline freestanding membranes from any compound materials with their excellent semiconducting performance. This technique is based on remote epitaxy of single-crystalline films on graphene followed by peeling from graphene. Stacking of freestanding 3D material membranes will enable unprecedented 3D heterostructures whose performance is expected to be superior to that of 2D heterostructures. I will talk about our group’s effort to apply single-crystalline freestanding membranes for flexible, conformal electronics as well as for 3D heterostructures. Finally, I will conclude my talk by discussing perspectives of coupling 2D-3D freestanding membranes for 2D-3D mixed heterostructured devices that can be enabled by our LRS and 2DLT techniques.

Kim, Jeehwan↗
DOE OSTI2022

III-V Solar Cells with Novel Epitaxial Lift-off Architectures for Extended Substrate Reuse for Low-cost Manufacturing

The highest solar cell efficiencies have been achieved with III-V photovoltaics (PV). Still, the use of III-V materials in terrestrial applications has been very limited, mainly because of their high cost. The high cost is primarily due to the expensive Ge or GaAs wafers which could amount up to one-half of the total module cost! A prominent approach to reduce the impact of the high cost of substrates used for III-V PV is through re-use of the wafer substrates by Epitaxial Lift-Off (ELO). Typically, using a sacrificial layer such as AlAs, the device part of the cell is lifted off, leaving behind the substrate for re-use for fabrication of the next device. While conversion efficiency as high as 29.1% has been achieved by ELO method, chemical mechanical polishing (CMP) of the substrate is required which significantly adds to the overall solar cell cost. In this project, we have developed a novel ELO architecture for single junction gallium arsenide (GaAs) solar cells that will not require CMP of the substrate for re-use. Multiple reuses of GaAs wafers have been demonstrated with no CMP, without degradation in solar cell efficiency. Also, the solar cells have been successfully lifted off and transferred to inexpensive substrates with less than 2% change in efficiency. By elimination of the CMP process, which is the highest cost component of III-V solar cells made by conventional ELO method (~$10/W), and decreasing the substrate cost by multiple re-uses, the developed technology could be a leap forward in significantly reducing the cost of III-V photovoltaics.

14 SOLAR ENERGY↗
DOE OSTI2022

Geranium Photodiodes for Hard Xray Detection

This report summarizes the investigations engaged at UC Davis under subcontract B632083, as related to the LLNL-LDRD Project “High-Speed X-Ray Imager Arrays.” The first section entails work done within the Electrical and Computer Engineering (ECE) Department. The purpose of the work done so far is to understand photodiode design and which parameters are conducive to the design goals, which are: I: Maximize the detector quantum efficiency. The device must have a quantum efficiency of roughly 5% at 80 keV. II: Minimize temporal response. Collection time is limited to 1ns. All charge must be collected in that time. III: Minimize dark current. In this document, various photodiode parameters and designs are explored, and their impact on these goals are tabulated. In addition to these, various instruments that have been constructed for either testing these parameters or helping teammates with their experiments. The second section entails work done with the Materials Science Engineering (MSE) Department. In accordance with the proposed development of the germanium ROIC backside imagers, a critical step in the micromachining of these devices was the removal of the substrate on which the PIN junctions were epitaxially grown. A common technique for the micromachining of silicon wafers is the use of chemical etching alongside an “etch-stop” layer. In this technique, a chemical etchant will remove material until it reaches the etch-stop layer, at which the etch rate will drop significantly. This high selectivity (ratio of etch rates) allows any unevenness in the initial etching to be effectively smoothed away in the event that part of the wafer surface reaches the etch-stop layer sooner than another. An initial literature review found a paper by Divan et al. in which the authors used ion implantation to dope germanium wafers and achieve selectivity on the order of 100, sufficient for a reliable etch-stop.

42 ENGINEERING↗
DOE OSTI2022

2D material-based layer transfer: Challenges and opportunities

For future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, needs for flexibility and stackability of electronic products have substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to the thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically complaint and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. For the past few decades, many different strategies to mitigate such performance-mechanical compliance dilemma by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. In today’s talk, I will discuss about various strategies to realize such a dream electronic system and how these strategies unlock new ways of manufacturing advanced electronic systems. One of the most promising approaches is to fabricate freestanding ultrathin membranes from existing functional material wafers by peeling the active layers from the top. I will overview all freestanding membrane methods and especially dive deeply into 2D materials-based layer transfer (2DLT) technique that has been recently emerging as one of the very promising options. In the 2DLT process, one can produce single-crystalline freestanding membranes from 3D materials by performing remote epitaxy or van der Waals epitaxy on 2D materials followed by peeling active single-crystalline films from the 2D materials. I will discuss about the challenges and opportunities of this technology. In addition, I will present unprecedented artificial heterostructures that can be enabled by stacking those freestanding 3D material membranes.

Kim, Jeehwan↗