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At least 415 records · Page 23

Performance Optimization Methods for a Memory-Bound, Unstructured-Grid CFD Application on Massively Parallel GPU Platforms

Computational performance of the FUN3D unstructured-grid computational fluid dynamics (CFD) application on massively parallel GPU environments is memory-bound and highly dependent upon efficient reads from and atomic updates to the irregular cell-, edge-, and node-based data structures. In this talk, we present recent efforts into optimizing select performance-critical kernels on NVIDIA Tesla V100 and A100 GPUs and AMD CDNA MI100 GPUs. A novel use of L2 cache residency controls and asynchronous loads into on-chip shared memory are explored on the A100 GPU for the sparse iterative solver, which is dominated by mixed-precision, sparse matrix vector multiplication. Demonstrations show that these methods improve global memory bandwidth utilization by 13.5% on the A100 GPU. Several techniques are also presented that use registers and/or shared memory to facilitate array transposition and aggregation which combine to reduce the frequency and increase the cache efficiency of floating-point atomic updates to the irregular data structures. These methods are demonstrated to improve the kernel throughput by nearly 500% on select kernels on the AMD MI100 over atomic updates directly to global memory. Overall, both V100 and A100 GPUs outperformed the MI100 GPU on kernels dominated by double-precision atomic updates; however, the techniques demonstrated here reduced the performance gap and improved the MI100 performance.

GPU CPU unstructured CFD memory↗

An iterative approach to region growing using associative memories

Region growing, often given as a classical example of the recursive control structures used in image processing which are often awkward to implement in hardware where the intent is the segmentation of an image at raster scan rates, is addressed in light of the postulate that any computation which can be performed recursively can be performed easily and efficiently by iteration coupled with association. Attention is given to an algorithm and hardware structure able to perform region labeling iteratively at scan rates. Every pixel is individually labeled with an identifier which signifies the region to which it belongs. Difficulties otherwise requiring recursion are handled by maintaining an equivalence table in hardware transparent to the computer, which reads the labeled pixels. A simulation of the associative memory has demonstrated its effectiveness.

Snyder, W. E.↗

A programmable computer interface for CAMAC

An interface has been developed for CAMAC instrumentation systems that implements data transfers controlled either by the computer CPU or by an autonomous (data-channel) processor in the interface unit. The data channel processor executes programs stored in the computer memory. These programs consist of standard CAMAC module commands plus special control characters and commands for the processor itself. The interface was built for the PDP-15 computer, which has an 18-bit word structure, but both 18- and 24-bit data transfers can be made. A software system has been written that exploits the many features of the processor.

Bercaw, R. W.↗

General-Purpose Serial Interface For Remote Control

Computer controls remote television camera. General-purpose controller developed to serve as interface between host computer and pan/tilt/zoom/focus functions on series of automated video cameras. Interface port based on 8251 programmable communications-interface circuit configured for tristated outputs, and connects controller system to any host computer with RS-232 input/output (I/O) port. Accepts byte-coded data from host, compares them with prestored codes in read-only memory (ROM), and closes or opens appropriate switches. Six output ports control opening and closing of as many as 48 switches. Operator controls remote television camera by speaking commands, in system including general-purpose controller.

Busquets, Anthony M.↗

Compact, Reliable EEPROM Controller

A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit.

Katz, Richard↗

All-Electric Nonassociative Learning in Nickel Oxide

Habituation and sensitization represent nonassociative learning mechanisms in both non-neural and neural organisms. They are essential for a range of functions from survival to adaptation in dynamic environments. Design of hardware for neuroinspired computing strives to emulate such features driven by electric bias and can also be incorporated into neural network algorithms. Herein, cellular-like learning in oxygen-deficient NiO x devices is demonstrated. Both habituation learning and sensitization response can be achieved in a single device by simply controlling the magnitude of the electric field. Spontaneous memory relaxations and dynamic redistribution of oxygen vacancies under electric bias enable such learning behavior of NiO x under sequential training. These characteristics in simple device arrays are implemented to learn alphabets as well as demonstrate simulated algorithmic use cases in digit recognition. Transition metal oxides with carefully prepared defect concentrations can be highly sensitive to electronic structure perturbations under moderate electrical stimulus and serve as building blocks for next-generation neuroinspired computing hardware.

36 MATERIALS SCIENCE↗

Sheath transitions in a cylindrical filament discharge: Axisymmetric 1D3V PIC-MCC simulations

We present the first nonplanar hot cathode discharge simulations that capture the role of the trapped-ions plasma, elucidating new phenomena unobservable in planar geometric discharges. A discharge struck between a single emitting wire filament cathode and a bounding anode is simulated in cylindrical geometry using an axisymmetric (radial) particle-in-cell Monte-Carlo collisions code. Operating the discharge near its ionization energy threshold can lead to the formation of a two plasma mode (TPM). One plasma forms in the conventional upstream region through electron impact ionization of background neutrals. A second plasma, whose global effect on the discharge was not previously well understood, forms downstream through the trapping of cold ions in the potential well of the filament’s virtual cathode, a process enabled by ion-neutral charge exchange collisions. Three space charge regions intersperse the electrode gap—an emissive sheath between the cathode filament and trapped-ions plasma, a double layer between the two plasmas, and a classical sheath between the upstream plasma and the outer anode. Simulations exhibit mode transitions and quenching instabilities that transform the discharge between the TPM and other single-plasma sheath modes that include classical (temperature-limited), space charge limited, and inverse (anode glow) modes. The transitions are explained via “aid-and-compete” dynamics wherein the growth of one plasma enhances growth in the other while concurrently exhibiting expansion dynamics antagonistic to each other. The system exhibits strong hysteresis memory during the mode transitions. Improved understanding and control of these sheath mode transitions are expected to benefit plasma applications with hot cathodes.

Electrical hysteresis↗

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

Hamilton, M. H.↗

Design, fabrication, testing and delivery of a feasibility model laminated ferrite memory

The effect of using multiword addressing with laminated ferrite arrays was made. Both a reduction in the number of components, and a reduction in power consumption was obtained for memory capacities between one million bits and one million words. An investigation into the effect of variations in the processing steps resulted in a number of process modifications that improved the quality of the arrays. A feasibility model laminated ferrite memory system was constructed by modifying a commercial plated wire memory system to operate with laminated ferrite arrays. To provide flexibility for the testing of the laminated ferrite memory, an exerciser has been constructed to automatically control the loading and recirculation of arbitrary size checkerboard patterns of one's and zero's and to display the patterns of stored information on a CRT screen.

Heckler, H. C.↗

Computer-controlled environmental test systems - Criteria for selection, installation, and maintenance.

Applications for presently marketed, new computer-controlled environmental test systems are suggested. It is shown that capital costs of these systems follow an exponential cost function curve that levels out as additional applications are implemented. Some test laboratory organization changes are recommended in terms of new personnel requirements, and facility modification are considered in support of a computer-controlled test system. Software for computer-controlled test systems are discussed, and control loop speed constraints are defined for real-time control functions. Suitable input and output devices and memory storage device tradeoffs are also considered.

Chapman, C. P.↗

An interface between a datametrics 1085A manometer and a Hewlett-Packard 2100S computer

A hardware/software interface designed to mate a Datametrics models 1085A electronic manometer to a Hewlett-Packard (HP) model 2100S computer is described. The software driver operates in the basic control system (BCS) and requires 173 words of memory; the hardware interface uses an HP data source interface (DSI) card which requires one computer input/output channel. Results obtained by incorporating this interface into a data acquisition system indicate that the interface operates successfully.

Hillard, M. E., Jr.↗

The PDS-VAX intelligent plate scanning system of Trieste Astronomical Observatory

An intelligent subsystem for interfacing a PDS1010A digital microdensitometer to a DEC DR11W DMA 16 bit UNIBUS port in DEC VAX VMS environment was tested. The subsystem employs two MOTOROLA M68000 microprocessors with 128 KB data memory. The PDS primitives and the user defined high level scanning functions and preprocessing modules are loaded from the host computer into two 8 KB RAM memories in the microprocessors using a dedicated PDS control language. The subsystem is planned to employ a nonstandard photomultiplier electronics. Two design schemes were tested: (1) based on three amplifiers of gain 10 cascaded and multiplexed to a 12 bit AD converter, and (2) based on a single amplifier of gain 100 and two 14 bit AD converters.

Pucillo, M.↗

Future MAUS payload and the TWIN-MAUS configuration

The German MAUS project (materials science autonomous experiments in weightlessness) was initiated in 1979 for optimum utilization of NASA's Get Away Special (GAS) program. The standard MAUS system was developed to meet GAS requirements and can accommodate a wide variety of GAS-type experiments. The system offers a range of services to experimenters within the framework of standardized interfaces. Four MAUS payloads being prepared for future space shuttle flight opportunities are described. The experiments include critical Marangoni convection, oscillatory Marangoni convection, pool boiling, and gas bubbles in glass melts. Scientific objectives as well as equipment hardware are presented together with recent improvements to the MAUS standard system, e.g., a new experiment control and data management unit and a semiconductor memory. A promising means of increasing resources in the field of GAS experiments is the interconnection of GAS containers. This important feature has been studied to meet the challenge of future advanced payloads. In the TWIN-MAUS configuration, electrical power and data will be transferred between two containers mounted adjacent to each other.

Staniek, S.↗

Solid-state thin-film memistor for electronic neural networks

This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Thakoor, S.↗

An area model for on-chip memories and its application

An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.

Mulder, Johannes M.↗

A set-associative, fault-tolerant cache design

The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.

Lamet, Dan↗