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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗
NASA NTRS1982

Off-line, built-in test techniques for VLSI circuits

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Buehler, M. G.↗
NASA NTRS1997

Logic Design Pathology and Space Flight Electronics

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Katz, Richard↗
NASA NTRS2009

The Diagnostic Challenge Competition: Probabilistic Techniques for Fault Diagnosis in Electrical Power Systems

Reliable systems health management is an important research area of NASA. A health management system that can accurately and quickly diagnose faults in various on-board systems of a vehicle will play a key role in the success of current and future NASA missions. We introduce in this paper the ProDiagnose algorithm, a diagnostic algorithm that uses a probabilistic approach, accomplished with Bayesian Network models compiled to Arithmetic Circuits, to diagnose these systems. We describe the ProDiagnose algorithm, how it works, and the probabilistic models involved. We show by experimentation on two Electrical Power Systems based on the ADAPT testbed, used in the Diagnostic Challenge Competition (DX 09), that ProDiagnose can produce results with over 96% accuracy and less than 1 second mean diagnostic time.

Ricks, Brian W.↗
DOE OSTI2024

Design considerations of series type hybrid circuit breaker (S‐HCB)

Abstract The series‐type direct current (DC) hybrid circuit breaker (S‐HCB) concept was previously reported to offer better performance than solid‐state circuit breakers (SSCB) and hybrid circuit breakers (HCB). S‐HCB offers low conduction power loss like an HCB and ‐scale interruption time, which is even faster than an SSCB. It uses a pulse transformer to isolate the lower‐voltage high‐inductance power electronic circuit from the high‐voltage, low‐inductance main power loop. This paper provides analysis of the impact of the S‐HCB circuit components on the overall system performance and a scalable S‐HCB design guide for different DC system voltage and current ratings. In addition, system energy flow analysis is performed in the time domain to provide an understanding of how energy is delivered, dissipated, and released throughout the entire fault interruption process. The S‐HCB prototype was experimentally tested at 3 kV/30 A and 6 kV/150A with the results showing the interruption of the low fault current of 30 A and the high fault current of 150 A within 8 and maintaining the fault current at a near zero value for 300 to enable an arcless opening of a series mechanical switch. The key design challenges of S‐HCB at high voltage and high current ratings were discussed and possible solutions to mitigate those challenges were introduced.

Alashi, Mahmoud↗
NASA NTRS1995

DRS: Derivational Reasoning System

The high reliability requirements for airborne systems requires fault-tolerant architectures to address failures in the presence of physical faults, and the elimination of design flaws during the specification and validation phase of the design cycle. Although much progress has been made in developing methods to address physical faults, design flaws remain a serious problem. Formal methods provides a mathematical basis for removing design flaws from digital systems. DRS (Derivational Reasoning System) is a formal design tool based on advanced research in mathematical modeling and formal synthesis. The system implements a basic design algebra for synthesizing digital circuit descriptions from high level functional specifications. DRS incorporates an executable specification language, a set of correctness preserving transformations, verification interface, and a logic synthesis interface, making it a powerful tool for realizing hardware from abstract specifications. DRS integrates recent advances in transformational reasoning, automated theorem proving and high-level CAD synthesis systems in order to provide enhanced reliability in designs with reduced time and cost.

Bose, Bhaskar↗
NASA NTRS2009

Developing Large-Scale Bayesian Networks by Composition: Fault Diagnosis of Electrical Power Systems in Aircraft and Spacecraft

In this paper, we investigate the use of Bayesian networks to construct large-scale diagnostic systems. In particular, we consider the development of large-scale Bayesian networks by composition. This compositional approach reflects how (often redundant) subsystems are architected to form systems such as electrical power systems. We develop high-level specifications, Bayesian networks, clique trees, and arithmetic circuits representing 24 different electrical power systems. The largest among these 24 Bayesian networks contains over 1,000 random variables. Another BN represents the real-world electrical power system ADAPT, which is representative of electrical power systems deployed in aerospace vehicles. In addition to demonstrating the scalability of the compositional approach, we briefly report on experimental results from the diagnostic competition DXC, where the ProADAPT team, using techniques discussed here, obtained the highest scores in both Tier 1 (among 9 international competitors) and Tier 2 (among 6 international competitors) of the industrial track. While we consider diagnosis of power systems specifically, we believe this work is relevant to other system health management problems, in particular in dependable systems such as aircraft and spacecraft. (See CASI ID 20100021910 for supplemental data disk.)

Mengshoel, Ole Jakob↗
DOE OSTI2025

Monocrystalline CdSeTe/MgCdTe Double‐Heterostructure Solar Cells

This article reports monocrystalline CdSeTe/MgCdTe double‐heterostructure (DH) solar cells with varying Se compositions in the absorber layers that are grown on InSb substrates by using molecular beam epitaxy. The Se composition in the samples studied is determined to be 4%–11% through high‐resolution X‐ray diffraction (XRD) and photoluminescence measurements. Increased Se incorporation induces higher defect density attributed to increased lattice mismatch, and mixed‐phase formation due to the small difference in formation energies between the wurtzite and zinc blende phases of CdSe, which causes stacking faults and grain boundaries. Devices are fabricated by directly depositing an n‐type indium tin oxide (ITO) layer on the CdSeTe/MgCdTe DHs followed by Ag metal contacts. Reduced bandgap is observed in solar cells with increased Se composition. The devices with an absorber containing 4% Se exhibit an average open‐circuit voltage ( V OC ) of 0.925 V, a short‐circuit current density ( J SC ) of 23.4 mA/cm 2 , a fill factor ( FF ) of 0.650 and an efficiency of 14.1% without anti‐reflection coating. Absorbers with higher Se compositions result in poor device performance, mainly attributed to high defect density in the materials.

Ju, Zheng [Center for Photonics Innovation Arizona↗
NASA NTRS1991

Development and testing of a 180-volt dc electronic circuit breaker with a 335-ampere carry and 1200-ampere interrupt rating

NASA Lewis Research Center and associated contractors have conducted a program to assess the potential requirements for a high-current switch to conceptually design a switch using the best existing technology, and to build and demonstrate a breadboard which meets the requirements. The result is the high current remote bus isolator (HRBI). The HRBI is rated at 180 V dc, 335 A continuous with a 1200 A interrupt rating. It also incorporates remote-control and protective features called for by the Space Station Freedom PMAD dc test bed design. Two breadboard 335 A circuit breakers were built and tested that demonstrate a promising concept of paralleled current-limiting modules. The units incorporated all control and protective features required by advanced aerospace power systems. Component stresses in each unit were determined by design, and are consistent with a life of many thousands of fault operations.

Brush, A. S.↗
DOE OSTI2021

Determining quantum phase diagrams of topological Kitaev-inspired models on NISQ quantum hardware

Topological protection is employed in fault-tolerant error correction and in developing quantum algorithms with topological qubits. But, topological protection intrinsic to models being simulated , also robustly protects calculations, even on NISQ hardware. We leverage it by simulating Kitaev-inspired models on IBM quantum computers and accurately determining their phase diagrams. This requires constructing conventional quantum circuits for Majorana braiding to prepare the ground states of Kitaev-inspired models. The entanglement entropy is then measured to calculate the quantum phase boundaries. We show how maintaining particle-hole symmetry when sampling through the Brillouin zone is critical to obtaining high accuracy. This work illustrates how topological protection intrinsic to a quantum model can be employed to perform robust calculations on NISQ hardware, when one measures the appropriate protected quantum properties. It opens the door for further simulation of topological quantum models on quantum hardware available today.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2012

Soldering in a Reduced Gravity Environment (SoRGE)

Future long-duration human exploration missions will be challenged by constraints on mass and volume allocations available for spare parts. Addressing this challenge will be critical to the success of these missions. As a result, it is necessary to consider new approaches to spacecraft maintenance and repair that reduce the need for large replacement components. Currently, crew members on the International Space Station (ISS) recover from faults by removing and replacing, using backup systems, or living without the function of Orbital Replacement Units (ORUs). These ORUs are returned to a depot where the root cause of the failure is determined and the ORU is repaired. The crew has some limited repair capability with the Modulation/DeModulation (MDM) ORU, where circuit cards are removed and replace in faulty units. The next step to reducing the size of the items being replaced would be to implement component-level repair. This mode of repair has been implemented by the U.S. Navy in an operational environment and is now part of their standard approach for maintenance. It is appropriate to consider whether this approach can be adapted for future spaceflight operations. To this end, the Soldering in a Reduced Gravity Environment (SoRGE) experiment studied the effect of gravity on the formation of solder joints on electronic circuit boards. This document describes the SoRGE experiment, the analysis methods, and results to date. This document will also contain comments from the crew regarding their experience conducting the SoRGE experiment as well as recommendations for future improvements. Finally, this document will discuss the plans for the SoRGE samples which remain on ISS.

Easton, John W.↗
DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗
NASA NTRS1971

Logic design for dynamic and interactive recovery.

Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.

Carter, W. C.↗
NASA NTRS2012

Compact, Low-Force, Low-Noise Linear Actuator

Actuators are critical to all the robotic and manipulation mechanisms that are used in current and future NASA missions, and are also needed for many other industrial, aeronautical, and space activities. There are many types of actuators that were designed to operate as linear or rotary motors, but there is still a need for low-force, low-noise linear actuators for specialized applications, and the disclosed mechanism addresses this need. A simpler implementation of a rotary actuator was developed where the end effector controls the motion of a brush for cleaning a thermal sensor. The mechanism uses a SMA (shape-memory alloy) wire for low force, and low noise. The linear implementation of the actuator incorporates a set of springs and mechanical hard-stops for resetting and fault tolerance to mechanical resistance. The actuator can be designed to work in a pull or push mode, or both. Depending on the volume envelope criteria, the actuator can be configured for scaling its volume down to 4 2 1 cm3. The actuator design has an inherent fault tolerance to mechanical resistance. The actuator has the flexibility of being designed for both linear and rotary motion. A specific configuration was designed and analyzed where fault-tolerant features have been implemented. In this configuration, an externally applied force larger than the design force does not damage the active components of the actuator. The actuator housing can be configured and produced using cost-effective methods such as injection molding, or alternatively, its components can be mounted directly on a small circuit board. The actuator is driven by a SMA -NiTi as a primary active element, and it requires energy on the order of 20 Ws(J) per cycle. Electrical connections to points A and B are used to apply electrical power in the resistive NiTi wire, causing a phase change that contracts the wire on the order of 5%. The actuation period is of the order of a second for generating the stroke, and 4 to 10 seconds for resetting. Thus, this design allows the actuator to work at a frequency of up to 0.1 Hz. The actuator does not make use of the whole range of motion of the SMA material, allowing for large margins on the mechanical parameters of the design. The efficiency of the actuator is of the order of 10%, including the margins. The average dissipated power while driving at full speed is of the order of 1 W, and can be scaled down linearly if the rate of cycling is reduced. This design produces an extremely quiet actuator; it can generate a force greater than 2 N and a stroke greater than 1 cm. The operational duration of SMA materials is of the order of millions of cycles with some reduced stroke over a wide temperature range up to 150 C.

Badescu, Mircea↗
NASA NTRS2012

Compact, Low-Force, Low-Noise Linear Actuator

Actuators are critical to all the robotic and manipulation mechanisms that are used in current and future NASA missions, and are also needed for many other industrial, aeronautical, and space activities. There are many types of actuators that were designed to operate as linear or rotary motors, but there is still a need for low-force, low-noise linear actuators for specialized applications, and the disclosed mechanism addresses this need. A simpler implementation of a rotary actuator was developed where the end effector controls the motion of a brush for cleaning a thermal sensor. The mechanism uses a SMA (shape-memory alloy) wire for low force, and low noise. The linear implementation of the actuator incorporates a set of springs and mechanical hard-stops for resetting and fault tolerance to mechanical resistance. The actuator can be designed to work in a pull or push mode, or both. Depending on the volume envelope criteria, the actuator can be configured for scaling its volume down to 4x2x1 cu cm. The actuator design has an inherent fault tolerance to mechanical resistance. The actuator has the flexibility of being designed for both linear and rotary motion. A specific configuration was designed and analyzed where fault-tolerant features have been implemented. In this configuration, an externally applied force larger than the design force does not damage the active components of the actuator. The actuator housing can be configured and produced using cost-effective methods such as injection molding, or alternatively, its components can be mounted directly on a small circuit board. The actuator is driven by a SMA -NiTi as a primary active element, and it requires energy on the order of 20 Ws(J) per cycle. Electrical connections to points A and B are used to apply electrical power in the resistive NiTi wire, causing a phase change that contracts the wire on the order of 5%. The actuation period is of the order of a second for generating the stroke, and 4 to 10 seconds for resetting. Thus, this design allows the actuator to work at a frequency of up to 0.1 Hz. The actuator does not make use of the whole range of motion of the SMA material, allowing for large margins on the mechanical parameters of the design. The efficiency of the actuator is of the order of 10%, including the margins. The average dissipated power while driving at full speed is of the order of 1 W, and can be scaled down linearly if the rate of cycling is reduced. This design produces an extremely quiet actuator; it can generate a force greater than 2 N and a stroke greater than 1 cm. The operational duration of SMA materials is of the order of millions of cycles with some reduced stroke over a wide temperature range up to 150 C.

Badescu, Mircea↗
NASA NTRS2004

Power Actuation and Switching Module Development

The Deep Space Avionics (DSA) Project is developing a Power Actuation and Switching Module (PASM). This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an A SIC process that is tolerant of high radiation. The development includes two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs, It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Threeway majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper describes the development process used to design, model, fabricate, and test these compact and versatile power switches. Preliminary test results from prototype HDI PASM hardware are also discussed.

Power Actuation and Switching Module (PASM)↗
DOE OSTI2020

Design of BLDC Motor Diagnostic Device Based on Surge Test for Phase to Ground Fault

BLDC motor is essential in the industrial world, especially it been used for an electric vehicle. The benefit of using BLDC motor is that it has high rate efficiency and low mechanical losses. However, to know the isolation condition of winding and increase reliability, it needs to be tested. With the implementation of surge test based fault detection device of BLDC motor, the condition of BLDC motor can be monitored and maintained according to analysis of its condition. The surge test method used because it is sensitive in detecting the initial damage in the isolation failure process on stator winding. A surge voltage is generated from the Cockroft-Walton and switching circuit with capacitors. The result is analyzed using Error Area Ratio (EAR). The test result shows that the higher the value of resistance and inductance, the smaller the frequency of the surge wave. When the BLDC motor in a parallel short circuit condition, the threshold value of the EAR test-reff has a minimum value of 5.28%, an average of 13.52%, and a maximum of 28.55%.

BLDC motor↗
DOE OSTI2025

Realizing string-net condensation: Fibonacci anyon braiding for universal gates and sampling chromatic polynomials

Abstract The remarkable complexity of a topologically ordered many-body quantum system is encoded in the characteristics of its anyons. Quintessential predictions emanating from this complexity employ the Fibonacci string net condensate (Fib SNC) and its anyons: sampling Fib-SNC would estimate chromatic polynomials while exchanging its anyons would implement universal quantum computation. However, physical realizations remained elusive. We introduce a scalable dynamical string net preparation (DSNP) that constructs Fib SNC and its anyons on reconfigurable graphs suitable for near-term superconducting processors. Coupling the DSNP approach with composite error-mitigation on deep circuits, we create, measure, and braids Fibonacci anyons; charge measurements show 94% accuracy, and exchanging the anyons yields the expected golden ratioϕwith 98% average accuracy. We then sample the Fib SNC to estimate chromatic polynomial atϕ + 2 for several graphs. Our results establish the proof of principle for using Fib-SNC and its anyons for fault-tolerant universal quantum computation and aim at a classically hard problem.

Science & Technology - Other Topics↗