Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “circuit complexity”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Charge-Control Unit for Testing Lithium-Ion Cells

A charge-control unit was developed as part of a program to validate Li-ion cells packaged together in batteries for aerospace use. The lithium-ion cell charge-control unit will be useful to anyone who performs testing of battery cells for aerospace and non-aerospace uses and to anyone who manufacturers battery test equipment. This technology reduces the quantity of costly power supplies and independent channels that are needed for test programs in which multiple cells are tested. Battery test equipment manufacturers can integrate the technology into their battery test equipment as a method to manage charging of multiple cells in series. The unit manages a complex scheme that is required for charging Li-ion cells electrically connected in series. The unit makes it possible to evaluate cells together as a pack using a single primary test channel, while also making it possible to charge each cell individually. Hence, inherent cell-to-cell variations in a series string of cells can be addressed, and yet the cost of testing is reduced substantially below the cost of testing each cell as a separate entity. The unit consists of electronic circuits and thermal-management devices housed in a common package. It also includes isolated annunciators to signal when the cells are being actively bypassed. These annunciators can be used by external charge managers or can be connected in series to signal that all cells have reached maximum charge. The charge-control circuitry for each cell amounts to regulator circuitry and is powered by that cell, eliminating the need for an external power source or controller. A 110-VAC source of electricity is required to power the thermal-management portion of the unit. A small direct-current source can be used to supply power for an annunciator signal, if desired.

Reid, Concha M.↗
NASA NTRS2010

Evaluation of Grounding Impedance of a Complex Lightning Protective System Using Earth Ground Clamp Measurements and ATP Modeling

A new Lightning Protection System (LPS) was designed and built at Launch Complex 39B (LC39B), at the Kennedy Space Center (KSC), Florida, which consists of a catenary wire system (at a height of about 181 meters above ground level) supported by three insulators installed atop three towers in a triangular configuration. A total of nine downconductors (each about 250 meters long, on average) are connected to the catenary wire system. Each of the nine downconductors is connected to a 7.62-meter radius circular counterpoise conductor with six equally spaced 6-meter long vertical grounding rods. Grounding requirements at LC39B call for all underground and above ground metallic piping, enclosures, raceways, and cable trays, within 7.62 meters of the counterpoise, to be bounded to the counterpoise, which results in a complex interconnected grounding system, given the many metallic piping, raceways, and cable trays that run in multiple direction around LC39B. The complexity of this grounding system makes the fall of potential method, which uses multiple metallic rods or stakes, unsuitable for measuring the grounding impedances of the downconductors. To calculate the downconductors grounding impedance, an Earth Ground Clamp (a stakeless grounding resistance measuring device) and a LPS Alternative Transient Program (ATP) model are used. The Earth Ground Clamp is used to measure the loop impedance plus the grounding impedance of each downconductor and the ATP model is used to calculate the loop impedance of each downconductor circuit. The grounding impedance of the downconductors is then calculated by subtracting the ATP calculated loop impedances from the Earth Ground Clamp measurements.

Mata, Carlos T.↗
NASA NTRS1987

Delay line anodes for microchannel-plate spectrometers

A photon-counting readout system for microchannel-plate spectrometers is described that uses a delay line and timing circuit for the wavelength coordinate and a wedge-wedge charge division system for the orthogonal spatial coordinate. A novel zigzag layout allows these two anode patterns to coexist on a common planar substrate and share the charge from each photoevent, thereby simultaneously localizing the photon in each of its two dimensions. Unlike wedge-and-strip or resistive anode encoders, the delay line offers a spatial resolution that is relatively independent of the format length. Unlike discrete anode systems, the delay line readout system's complexity is also independent of the field of view size. These facts make the delay line readout system advantageous in large format detectors. A testbed detector having a delay line propagation speed of 2.2 mm/ns and a time resolution of 33 ps FWHM has been assembled. Ultraviolet testing shows a Gaussian event distribution having a 70-micron FWHM width; the readout system blur contribution is less than 50-micron FWHM.

Lampton, M.↗
NASA NTRS1982

Simplification of power electronics for ion thruster neutralizers

A need exists for less complex and lower cost ion thruster systems. Design approaches and the demonstration of neutralizer power electronics for relaxed neutralizer keeper, tip heater, and vaporizer requirements are discussed. The neutralizer circuitry is operated from a 200 to 400 V bus and demonstrates an order of magnitude reduction in parts count. Furthermore, a new technique is described for regulating tip heater power and automatically switching over to provide keeper power with only four additional components. A new design to control the flow rate of the neutralizer with one integrated circuit is also presented.

Gruber, R. P.↗
NASA NTRS2002

Microwave Power for Smart Membrane Actuators

The concept of microwave-driven smart membrane actuators is envisioned as the best option to alleviate the complexity associated with hard-wired control circuitry. A large, ultra-light space structure, such as solar sails and Gossamer spacecrafts, requires a distribution of power into individual membrane actuators to control them in an effective way. A patch rectenna array with a high voltage output was developed to drive smart membrane actuators. Networked patch rectenna array receives and converts microwave power into a DC power for an array of smart actuators. To use microwave power effectively, the concept of a power allocation and distribution (PAD) circuit is developed and tested for networking a rectenna/actuator patch array. For the future development, the PAD circuit could be imbedded into a single embodiment of rectenna and actuator array with the thin-film microcircuit embodiment. Preliminary design and fabrication of PAD circuitry that consists of a sixteen nodal elements were made for laboratory testing.

Choi, Sang H.↗
NASA NTRS2012

Sample-Clock Phase-Control Feedback

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.

Quirk, Kevin J.↗
NASA NTRS2017

Modeling for Battery Prognostics

For any battery-powered vehicles (be it unmanned aerial vehicles, small passenger aircraft, or assets in exoplanetary operations) to operate at maximum efficiency and reliability, it is critical to monitor battery health as well performance and to predict end of discharge (EOD) and end of useful life (EOL). To fulfil these needs, it is important to capture the battery's inherent characteristics as well as operational knowledge in the form of models that can be used by monitoring, diagnostic, and prognostic algorithms. Several battery modeling methodologies have been developed in last few years as the understanding of underlying electrochemical mechanics has been advancing. The models can generally be classified as empirical models, electrochemical engineering models, multi-physics models, and molecular/atomist. Empirical models are based on fitting certain functions to past experimental data, without making use of any physicochemical principles. Electrical circuit equivalent models are an example of such empirical models. Electrochemical engineering models are typically continuum models that include electrochemical kinetics and transport phenomena. Each model has its advantages and disadvantages. The former type of model has the advantage of being computationally efficient, but has limited accuracy and robustness, due to the approximations used in developed model, and as a result of such approximations, cannot represent aging well. The latter type of model has the advantage of being very accurate, but is often computationally inefficient, having to solve complex sets of partial differential equations, and thus not suited well for online prognostic applications. In addition both multi-physics and atomist models are computationally expensive hence are even less suited to online application An electrochemistry-based model of Li-ion batteries has been developed, that captures crucial electrochemical processes, captures effects of aging, is computationally efficient, and is of suitable accuracy for reliable EOD prediction in a variety of operational profiles. The model can be considered an electrochemical engineering model, but unlike most such models found in the literature, certain approximations are done that allow to retain computational efficiency for online implementation of the model. Although the focus here is on Li-ion batteries, the model is quite general and can be applied to different chemistries through a change of model parameter values. Progress on model development, providing model validation results and EOD prediction results is being presented.

Prognostics↗
NASA NTRS2012

Calculating the Lightning Protection System Downconductors' Grounding Resistance at Launch Complex 39B, Kennedy Space Center

A new Lightning Protection System (LPS) was designed and built at Launch Complex 39B (LC39B), at the Kennedy Space Center (KSC), Florida, which consists of a catenary wire system (at a height of about 181 meters above ground level) supported by three insulators installed atop three towers in a triangular configuration. Nine downconductors (each about 250 meters long) are connected to the catenary wire system. Each downconductor is connected to a 7.62-meter-radius circular counterpoise conductor with six equally spaced, 6-meter-long vertical grounding rods. Grounding requirements at LC39B call for all underground and aboveground metallic piping, enclosures, raceways, and cable trays, within 7.62 meters of the counterpoise, to be bonded to the counterpoise, which results in a complex interconnected grounding system, given the many metallic piping, raceways, and cable trays that run in multiple directions around LC39B. The complexity of this grounding system makes the fall-of-potential method, which uses multiple metallic rods or stakes, unsuitable for measuring the grounding impedances of the downconductors. To calculate the grounding impedance of the downconductors, an Earth Ground Clamp (EGC) (a stakeless device for measuring grounding impedance) and an Alternative Transient Program (ATP) model of the LPS are used. The EGC is used to measure the loop impedance plus the grounding impedance of each downconductor, and the ATP model is used to calculate the loop impedance of each downconductor circuit. The grounding resistance of the downconductors is then calculated by subtracting the ATP calculated loop impedances from the EGC measurements.

Mata, Carlos T.↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2004

NASA Tech Briefs, April 2004

Topics covered include: Analysis of SSEM Sensor Data Using BEAM; Hairlike Percutaneous Photochemical Sensors; Video Guidance Sensors Using Remotely Activated Targets; Simulating Remote Sensing Systems; EHW Approach to Temperature Compensation of Electronics; Polymorphic Electronic Circuits; Micro-Tubular Fuel Cells; Whispering-Gallery-Mode Tunable Narrow-Band-Pass Filter; PVM Wrapper; Simulation of Hyperspectral Images; Algorithm for Controlling a Centrifugal Compressor; Hybrid Inflatable Pressure Vessel; Double-Acting, Locking Carabiners; Position Sensor Integral with a Linear Actuator; Improved Electromagnetic Brake; Flow Straightener for a Rotating-Drum Liquid Separator; Sensory-Feedback Exoskeletal Arm Controller; Active Suppression of Instabilities in Engine Combustors; Fabrication of Robust, Flat, Thinned, UV-Imaging CCDs; Chemical Thinning Process for Fabricating UV-Imaging CCDs; Pseudoslit Spectrometer; Waste-Heat-Driven Cooling Using Complex Compound Sorbents; Improved Refractometer for Measuring Temperatures of Drops; Semiconductor Lasers Containing Quantum Wells in Junctions; Phytoplankton-Fluorescence-Lifetime Vertical Profiler; Hexagonal Pixels and Indexing Scheme for Binary Images; Finding Minimum-Power Broadcast Trees for Wireless Networks; and Automation of Design Engineering Processes.

Source record↗
NASA NTRS2007

Flexible Skins Containing Integrated Sensors and Circuitry

Artificial sensor skins modeled partly in imitation of biological sensor skins are undergoing development. These sensor skins comprise flexible polymer substrates that contain and/or support dense one- and two-dimensional arrays of microscopic sensors and associated microelectronic circuits. They afford multiple tactile sensing modalities for measuring physical phenomena that can include contact forces; hardnesses, temperatures, and thermal conductivities of objects with which they are in contact; and pressures, shear stresses, and flow velocities in fluids. The sensor skins are mechanically robust, and, because of their flexibility, they can be readily attached to curved and possibly moving and flexing surfaces of robots, wind-tunnel models, and other objects that one might seek to equip for tactile sensing. Because of the diversity of actual and potential sensor-skin design criteria and designs and the complexity of the fabrication processes needed to realize the designs, it is not possible to describe the sensor-skin concept in detail within this article.

Liu, Chang↗
NASA NTRS2011

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗
NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗
NASA NTRS1975

Packaging printed circuit boards: A production application of interactive graphics

The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.

Perrill, W. A.↗
NASA NTRS2015

Wideband Array for C, X, and Ku-Band Applications with 5.3:1 Bandwidth

Planar arrays that exploit strong intentional coupling between elements have allowed for very wide bandwidths in low-profile configurations. However, such designs also require complex impedance matching networks that must also be very compact. For many space applications, typically occurring at C-, X-, Ku-, and most recently at Ka-band, such designs require specialized and expensive fabrication techniques. To address this issue, a novel ultra-wideband array is presented, using a simplified feed network to reduce fabrication cost. The array operates from 3.5-18.5 GHz with VSWR less than 2.4 at broadside, and is of very low profile, having a total height of lambda/10 at the lowest frequency of operation. Validation is provided using a 64-element prototype array, fabricated using common Printed Circuit Board (PCB) technology. The low size, weight, and cost of this array make it attractive for space-borne applications.

X-↗
NASA NTRS2004

Parallel-Processing Equalizers for Multi-Gbps Communications

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel- processing digital receivers of multi-gigahertz radio signals and other quadrature-phase-shift-keying (QPSK) or 16-quadrature-amplitude-modulation (16-QAM) of data signals at rates of multiple gigabits per second. Equalizers as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application- specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates. A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

Gray, Andrew↗
NASA NTRS2011

MOSFET Switching Circuit Protects Shape Memory Alloy Actuators

A small-footprint, full surface-mount-component printed circuit board employs MOSFET (metal-oxide-semiconductor field-effect transistor) power switches to switch high currents from any input power supply from 3 to 30 V. High-force shape memory alloy (SMA) actuators generally require high current (up to 9 A at 28 V) to actuate. SMA wires (the driving element of the actuators) can be quickly overheated if power is not removed at the end of stroke, which can damage the wires. The new analog driver prevents overheating of the SMA wires in an actuator by momentarily removing power when the end limit switch is closed, thereby allowing complex control schemes to be adopted without concern for overheating. Either an integral pushbutton or microprocessor-controlled gate or control line inputs switch current to the actuator until the end switch line goes from logic high to logic low state. Power is then momentarily removed (switched off by the MOSFET). The analog driver is suited to use with nearly any SMA actuator.

Gummin, Mark A.↗
NASA NTRS1987

Dynamic characteristics of the national full-scale aerodynamic complex drive fan blades

An extensive experimental test program was conducted to define the dynamic characteristics of the newly installed fan blades of the NASA Ames 40- by 80-/80- by 120-Foot Wind Tunnel. The tests were intended to substantiate the blade design and manufacturing process, verify installation integrity, and guarantee safe fan-drive operation. The program included a shake test of each fan blade after installation and before operation as well as the monitoring of blade strain levels during initial operation. Structural characteristics, as determined by the shake test, include the modal frequency and damping values for elastic bending and torsion modes between 5 and 130 Hz. Operational testing defined the maximum and oscillatory blade-bending strains throughout the drive-system operational envelope. Results are presented for the shake test and initial operation of the 40- by 80-Foot Wind Tunnel circuit.

Peterson, Randall L.↗