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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

A Simple Control to Reduce the Voltage Stress of Non-Conducting Switches in Three-Level ANPC Converter

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices is increased, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage of non-conducting switches can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the over-voltage for the non-conducting switch. It is found that the nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing any additional hardware circuit is proposed to attenuate the impact of the nonlinearity. With the proposed control, the peak over-voltage of the non-conducting switch can be reduced significantly. Multi-pulse test is conducted for a 3L- ANPC converter built with silicon carbide (SiC) MOSFETs. The testing results show that the peak over-voltage decreases from 892 V to 624 V with the proposed control. More detailed analysis and experimental results will be provided in the final paper.

SiC MOSFET↗
DOE OSTI2023

Remarkable heat conduction mediated by non-equilibrium phonon polaritons

Surface waves can lead to intriguing transport phenomena. In particular, surface phonon polaritons (SPhPs), which result from coupling between infrared light and optical phonons, have been predicted to contribute to heat conduction along polar thin films and nanowires. However, experimental efforts so far suggest only very limited SPhP contributions. Through systematic measurements of thermal transport along the same 3C-SiC nanowires with and without a gold coating on the end(s) that serves to launch SPhPs, here we show that thermally excited SPhPs can substantially enhance the thermal conductivity of the uncoated portion of these wires. The extracted pre-decay SPhP thermal conductance is more than two orders of magnitude higher than the Landauer limit predicted on the basis of equilibrium Bose–Einstein distributions. Here, we attribute the notable SPhP conductance to the efficient launching of non-equilibrium SPhPs from the gold-coated portion into the uncoated SiC nanowires, which is strongly supported by the observation that the SPhP-mediated thermal conductivity is proportional to the length of the gold coating(s). The reported discoveries open the door for modulating energy transport in solids by introducing SPhPs, which can effectively counteract the classical size effect in many technologically important films and improve the design of solid-state devices.

42 ENGINEERING↗
NASA NTRS2000

Method For Growth of Crystal Surfaces and Growth of Heteroepitaxial Single Crystal Films Thereon

A method of growing atomically-flat surfaces and high quality low-defect crystal films of semiconductor materials and fabricating improved devices thereon is discussed. The method is also suitable for growing films heteroepitaxially on substrates that are different than the film. The method is particularly suited for growth of elemental semiconductors (such as Si), compounds of Groups III and V elements of the Periodic Table (such as GaN), and compounds and alloys of Group IV elements of the Periodic Table (such as SiC).

Powell, J. Anthony↗
DOE OSTI2024

Tailoring Growth Interfaces of Virtual Substrates for Power Electronics

Power electronics materials are poised to play a critical role in fulfilling next generation energy needs, with up to 90% of future energy demand predicted to flow through power electronics at some point. AlxGa1-xN ranks high among candidate materials, having bipolar dopability, thermal and chemical stability and an ultra-wide bandgap. However, AlGaN growth is limited by a lack of lattice-matched substrates, ultimately stunting material quality at higher thicknesses needed for power electronics applications. Further, high power applications increasingly call for fully vertical device structures, necessitating a conductive substrate. Recently our group identified the (111) plane of TaC as a conductive surface lattice-matched to Al0.55Ga0.45N, taking inspiration from prior work of AlN and GaN binaries on carbide and boride substrates. In this talk we demonstrate the growth of (111)-oriented TaC by RF sputtering. We investigate the interface of TaC with sapphire and SiC substrates and identify means to suppress competing Ta2C nucleation in order to stabilize (111)-oriented TaC. Potential stacking sequences are identified with respect to crystal structure and observed twinning in the TaC films. We next assess structural changes and film recrystallization that results from face-to-face annealing of TaC thin films at high temperatures above 1500 degrees C. Changes to grain structure and domain size are assessed by x-ray diffraction and surface morphology is explored using atomic force microscopy. Figure 1 shows significant improvements to in- and out-of-plane strain following annealing along with the formation of terraced step edges at the film surface. Strain as a function of material composition and thickness is considered, as this may play a major role in future nucleation of AlGaN layers. (1) R. J. in a face-to-face configuration, as illustrated in the schematic at left. Kaplar et al 2017, ECS J. Solid State Sci. Technol. 6 Q3061; (2) D. M. Roberts et al 2022, https://arxiv.org/abs/2208.11769; (3) T. Aizawa et al 2008, J Crys Growth 310, 1 22; (4) R. Liu et al 2002, Appl. Phys. Lett. 81, 3182-3184.

ENGINEERING↗
DOE OSTI2021

SiC-Based 5-kV Universal Modular Soft-Switching Solid-State Transformer (M-S4T) for Medium-Voltage DC Microgrids and Distribution Grids

Medium-voltage DC (MVDC) grids are attractive for electric aircraft and ship power systems, battery energy storage system (BESS), fast charging electric vehicle (EV), etc. Such EV or BESS applications need isolated bidirectional MVDC to LVDC or LVAC converters. However, the existing Si-based solutions cannot fulfill the requirements of a high-efficiency and robust converter for MVDC grids. This paper presents a 5 kV SiC-based universal modular solid-state transformer (SST). This universal current-source SST can interface either a LVAC or LVDC grid with a MVDC grid in single-stage power conversion, while the conventional dual active bridge (DAB) converter needs an additional inverter. The proposed SST module using 3.3 kV SiC MOSFETs and diodes is bidirectional and can serve as a building block in series or parallel for higher-voltage higher-power systems. The topology of each module is based on the soft-switching solid-state transformer (S4T) with reduced conduction loss, which features reduced EMI through controlled dv/dt, and high efficiency with full-range ZVS for main devices and ZCS for auxiliary devices. Operation principle of the modular S4T (M-S4T), capacitor voltage balancing control between the cascaded modules, design of components including a medium-voltage (MV) medium-frequency transformer (MFT) to realize a 50 kVA 5 kV DC to 600 V DC or 480 V AC M-S4T are presented. Importantly, the MV MFT prototype achieves very low leakage inductance (0.13%) and 15 kV insulation with coaxial cables and nanocrystalline cores. Here, the proposed universal modular SST is compared against the DAB solution and verified with DC-DC and DC-AC simulation and 4 kV experimental results. Significantly, the MV experimental results of a modular DC transformer with each module at MVDC are rarely covered in the literature and reported for the first time.

14 SOLAR ENERGY↗
DOE OSTI2024

Double-Side Cooled 1.2kV, 300A SiC MOSFET Phase-leg Modules for 200 kW, > 100 kW/L Traction Inverters

The packaging of a double-side cooled 1.2 kV, 149 A SiC phase-leg modules has been reported in recent years for making 100 kW, 100 kW/L traction inverters. Each phase-leg module consists of two SiC MOSFETs, one per switch position. Six of the phase-leg modules are assembled into a segmented inverter configuration to meet the power and power density requirement. In this work, the layout of the phase-leg module was redesigned to include four of the SiC MOSFETs, two per switch position, with the aim of doubling the power to 200 kW and increasing the power density beyond 100 kW/L, but with only a 10.25% footprint increase. Key features of the packaging technology developed in the previous work were implemented in the current work, which include silver sintering for chip bonding and porous silver inter-posts for bonding device source pads to substrate. Parasitic extraction simulation showed that the four-chip module has a low parasitic inductance of 4.7 nH, like the two-chip module. Static characterization of the four-chip prototypes showed a low average on-resistance of 9 mΩ and a low average leakage current of 5 nA at Vds of 1.2 kV.

Zhang, Zichen↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
DOE OSTI2024

Solid state protective smart plug device

A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.

Shen, Zheng↗
DOE OSTI2023

PV Inverter Systems Enabled by Monolithically Integrated SiC based Four Quadrant Power Switch (4-QPS) [BiDFET]

The purpose of this project was to develop a new breed of Power Conversion Systems (PCS) for PV integration that is enabled by the newly developed 4-Quadrant Single Die SiC Power Semiconductor Switches (4-QPS) or also referred to as “Bidirectional FET (BIDFET)”. This work includes semiconductor die development, advanced packaging, converter design, development, and testing of 4-QPS enabled hardware prototypes at 1 kW (for single phase residential application) and 10 kW (for three phase commercial application). The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

ARC-SAFE: Accelerated Response semiconducting Contactors and Surge Attenuation For DC Electrical systems (Final Scientific/Technical Report)

The landscape of power transmission and distribution is quickly evolving as more power conversion is done through power electronics and transmitted or distributed at medium voltage direct current (MVDC). As power electronics tend to store less energy and be less resilient to faults than conventional power transformers, a reliable and fast protection against faults is critical to protect power electronics (PE) based infrastructure, especially for medium- and high-voltage applications. This motivates the development of PE based protection circuits to replace slower contemporary electromechanical breakers. In this project a novel PE based MVDC circuit breaker is developed; the new design is comprised of 1) a normally-on leg made of commercially-available, cascaded SiC junction field effect transistors (JFETs) with a passive balancing network, and 2) a normally-off leg based on an optically-triggered gallium nitride (GaN) photoconductive semiconductor switch (PCSS). The normally-off leg was designed to be quickly turned on, to divert current to an auxiliary dissipative circuit, as the normally-on leg is turned off. This approach, using solid-state devices, was selected for a high-performance, fast-switching operation for the DC circuit breaker as compared to approaches that use slower mechanical switches. To be practical, the circuit breaker must have low conduction loss (low Ron) in the normally-on leg and fast coordinated triggering of the normally-off leg to avoid damage from inductive flyback, which could be considerable for long lengths of cable.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Tailoring Growth Interfaces of Virtual Substrates for Power Electronics

Power electronics materials are poised to play a critical role in fulfilling next generation energy needs, with up to 90% of future energy demand predicted to flow through power electronics at some point.[1] Among a number of candidate materials, AlxGa1-xN is the strongest, having bipolar dopability, thermal and chemical stability, an ultra-wide bandgap, and demonstrated experimental feasibility. However, AlGaN growth is limited by a lack of lattice-matched substrates, ultimately stunting material quality at higher thicknesses needed for power electronics applications. Further, high power applications increasingly call for fully vertical device structures, necessitating a conductive substrate. [1] Recently our group identified the (111) plane of TaC as a conductive surface lattice-matched to Al0.55Ga0.45N, taking inspiration from prior work of AlN and GaN binaries on carbide and boride substrates. [2,3,4] In this talk we demonstrate the growth of (111)-oriented TaC by RF sputtering. We investigate the interface of TaC with sapphire and SiC substrates and identify means to suppress competing Ta2C nucleation in order to stabilize (111)-oriented TaC. Potential stacking sequences are identified with respect to crystal structure and observed twinning in the TaC films. We next assess structural changes and film recrystallization that results from face-to-face annealing of TaC thin films at high temperatures above 1500 degrees Celsius. Changes to grain structure and domain size are assessed by x-ray diffraction and surface morphology is explored using atomic force microscopy. Figure 1 shows significant improvements to in- and out-of-plane strain following annealing along with the formation of terraced step edges at the film surface. Strain as a function of material composition and thickness is considered, as this may play a major role in future nucleation of AlGaN layers.

CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SU↗
DOE OSTI2024

Atomic-scale manipulation of buried graphene–silicon carbide interface by local electric field

Abstract Precision of scanning tunneling microscopy (STM) enables control of matter at scales of single atoms. However, transition from atomic-scale manipulation strategies to practical devices encounters fundamental problems in protection of the designer structures formed atop the surface. In this context, STM manipulation of subsurface structures on technologically relevant materials is encouraging. Here, we propose a material platform and protocols for precise manipulation of a buried graphene interface. We show that an electric field from the STM tip reversibly controls breaking and restoring of covalent bonds between the graphene buffer layer and the SiC substrate. The process involves charge redistribution at the atomically sharp interface plane under the epitaxial graphene layer(s). This buried manipulation platform is laterally defined by unit cells from the corresponding (6×6) SiC moiré lattice of the epitaxial graphene. Local and reversible electric-field-induced patterning of graphene heterostructures from the bottom interface creates an alternative architecture concept for their applications.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS2019

Long Duration Venus Probes and Landers

Planetary probes have long been a tool used by scientists to gain early clues on environments and systems of new planetary targets. This not only fueled the scientific process but also helped prepare for future missions, such as landers, and helped ensure their success. Venus, Earth's sister planet, has been the target of more probes and landers than any other body in our solar system except for Earth and yet many fundamental questions are unanswered. Challenge for Venus Surface Science: This lack of knowledge is a result of the challenging Venus environments. Remote sensing of the surface and portions of the atmosphere is difficult at best due to the thick layers of sulfuric acid clouds and the high pressure supercritical CO2 atmosphere below those clouds. This has hampered the ability of orbiting missions to provide us insight into surface features and processes and thus hides potential clues on interior process from our view. Surface probes and landers face an even more daunting challenge, which is the extreme temperature, pressure and unfriendly chemical composition of the near surface atmosphere. Over 10 assets have landed on the surface yet the longest surviving asset Venera-13 lasted only 127 minutes before succumbing to the extreme temperature. While this and other landers provided valuable new data, the short life impacted ability to understand any temporal processes, for example meteorology, seismic active, and therefore very little is known about the interior and surface atmosphere interactions. New Capability Offering Potential Solutions: Re-cent developments by NASA are offering hope of overcoming the technical challenges of surface operations and life with the use of high temperature electronics and systems. Wide band gap, SiC based electronics have been demonstrated to function successfully for extended periods of time both at 500C, Venus surface temperatures as well as when temperature is combined with the reactive chemistry of the surface atmosphere and the high pressures (over 90 bar pressure at the surface). In addition to electronics a number of other subsystems are in development including power in the form of high temperature batteries and power management devices, communications including antennas, transmitters and other components, materials, and structures and mechanisms. These are all activities under NASA's Long Lived In situ Solar System Exploration (LLISSE) project. Other activities are also funded under NASA's HOTTech program.

Kremic, T.↗
DOE OSTI2021

Multiscale Electrothermal Design of a Modular Multilevel Converter for Grid-Tied Applications

As a key feature of modular multilevel converters (MMCs), a large number of semiconductor devices are employed in the converter and distributed over a stack of submodules. Each submodule has a strict temperature limit that imposes constraints on the operating range of the converter. Different loading conditions/losses in the submodules lead to unavoidable temperature variations inside the MMC, which consequently affect the system-level performance and reliability. This paper is focused on the electrothermal analysis and design of a medium-voltage silicon carbide (SiC)-based MMC system, from submodule power semiconductors to the overall MMC system integration of multiple submodules. Loss calculations are performed to estimate the cooling requirements and aid thermal design at different levels. The performance of forced-air cooling approach is analyzed within a numerical modeling framework. Maximum temperature of the SiC power modules is predicted using numerical tools. Thermal design of the MMC cabinet with various arrangement of air inlet(s) and outlet(s) is investigated and compared from a cooling performance perspective.

CFD↗
DOE OSTI2025

Bismuthene Under Cover: Graphene Intercalation of a Large Gap Quantum Spin Hall Insulator

Abstract The quantum spin Hall insulator bismuthene, a two‐third monolayer of bismuth on SiC(0001), is distinguished by helical metallic edge states that are protected by a groundbreaking 800 meV topological gap, making it ideal for room temperature applications. This massive gap inversion arises from a unique synergy between flat honeycomb structure, strong spin orbit coupling, and an orbital filtering effect that is mediated by the substrate. However, the rapid oxidation of bismuthene in air has severely hindered the development of applications, so far confining experiments to ultra‐high vacuum conditions. Intercalating bismuthene between SiC and a protective sheet of graphene, this barrier is successfully overcome. As demonstrated by scanning tunneling microscopy and photoemission spectroscopy, graphene intercalation preserves the structural and topological integrity of bismuthene, while effectively shielding it from oxidation in air. Hereby, hydrogen is identified as the critical process gas that was missing in previous bismuth intercalation attempts. These findings facilitate ex‐situ experiments and pave the way for the development of bismuthene based devices, signaling a significant step forward in the development of next‐generation technologies.

Chemistry↗
DOE OSTI2023

Isolated Single-stage Three-phase AC/DC Converter using Bidirectional Switches

The advent of the SiC Bidirectional FET (BiDFET), a monolithic 1.2 kV bidirectional switch, has rendered the single-stage three-phase AC/DC converter topology a promising approach for implementing AC/DC converters. This topology, which integrates a full-bridge converter with a single-phase to three-phase matrix converter via a high-frequency transformer, is particularly suitable for applications requiring galvanic isolation, buck-boost functionality, and bidirectional power flow. The single-stage design eliminates the need for bulky and unreliable electrolytic capacitors, and utilizes a single magnetic component for power transfer. In the matrix converter, bidirectional switches, which were traditionally implemented using combinations of multiple semiconductor devices such as MOSFETs, IGBTs, and diodes, can now be realized using the single-chip solution, BiDFET. This advancement leads to a lower switch count, compact converter implementation, with lower inductance commutation cells, thereby enhancing the overall efficiency and compactness of the system. The paper presents a unified model of the converter, considering all control parameters, including the duty cycles and phase shift of transformer voltages. Detailed expressions for power transfer, transformer currents, and currents at AC and DC ports are provided. Additionally, the paper outlines the conditions necessary for soft-switching of all switches and the commutation schemes required for the practical implementation of the matrix converter modulation scheme. A hardware prototype of a 10 kW, 480 VRMS, LL/ 800 V AC/DC system has been developed, and experimental results are presented to demonstrate its performance.

BiDFET↗
NASA NTRS2006

Patches for Repairing Ceramics and Ceramic-Matrix Composites

Patches consisting mostly of ceramic fabrics impregnated with partially cured polymers and ceramic particles are being developed as means of repairing ceramics and ceramic-matrix composites (CMCs) that must withstand temperatures above the melting points of refractory metal alloys. These patches were conceived for use by space-suited, space-walking astronauts in repairing damaged space-shuttle leading edges: as such, these patches could be applied in the field, in relatively simple procedures, and with minimal requirements for specialized tools. These design characteristics also make the patches useful for repairing ceramics and CMCs in terrestrial settings. In a typical patch as supplied to an astronaut or repair technician, the polymer would be in a tacky condition, denoted as an A stage, produced by partial polymerization of a monomeric liquid. The patch would be pressed against the ceramic or CMC object to be repaired, relying on the tackiness for temporary adhesion. The patch would then be bonded to the workpiece and cured by using a portable device to heat the polymer to a curing temperature above ambient temperature but well below the maximum operating temperature to which the workpiece is expected to be exposed. The patch would subsequently become pyrolized to a ceramic/glass condition upon initial exposure to the high operating temperature. In the original space-shuttle application, this exposure would be Earth-atmosphere-reentry heating to about 3,000 F (about 1,600 C). Patch formulations for space-shuttle applications include SiC and ZrO2 fabrics, a commercial SiC-based pre-ceramic polymer, and suitable proportions of both SiC and ZrO2 particles having sizes of the order of 1 m. These formulations have been tailored for the space-shuttle leading-edge material, atmospheric composition, and reentry temperature profile so as to enable repairs to survive re-entry heating with expected margin. Other formulations could be tailored for specific terrestrial applications.

Hogenson, Peter A.↗
NASA NTRSDate not supplied

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗