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Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.
This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.
Stick module interconnection of flat packs into single-axis motherboard
Cleanliness validation of printed circuit assemblies has become increasingly important as electronic assemblies become smaller, denser, and more challenging to clean, prompting an increase in reliance in custom solutions. With increasingly fast paced development cycles, long lead times and costs of quality custom surrogate test boards become prohibitive in obtaining cleanliness data that is a true representative of the final product. In this study, aerosol jet printing, an additive manufacturing technology for electronics, was used to manufacture surface insulation resistance (SIR) test structures that were evaluated on their ability to detect cleanliness defects and remain stable when clean, as well as their survivability to standard electronics wash processes. Additionally, in an effort to further increase the agility of true product testing, SIR test structures were printed directly onto ball-grid-arrays (BGAs) and tested the survivability of conformally printed leads for data acquisition. SIR test structures displayed good wash survivability on standard FR4 and BGAs, including wraparounds for on-component prints, and high sensitivity to cleanliness defects. The presented results demonstrate the feasibility of printed SIR structures as a quick-turn, highly customizable solution for wash validation with potential for increased fidelity cleanliness testing.
An interactive computer-graphics-based tool for specifying the placement of electronic parts on a wire-wrap circuit board is presented. Input is a data file (currently produced by a commercial logic design system) which describes the parts used and their interconnections. Output includes printed reports describing the parts and wire paths, parts counts, placement lists, board drawing, and a tape to send to the wire-wrap vendor. The program should reduce the engineer's layout time by a factor of 3 to 5 as compared to manual methods.
An ultracapacitor made from a polymer loaded with ceramic powder would have several advantages over current ultracapacitors and batteries. First is the possibility of it being printable, which would allow for printing the energy storage device along with the circuit instead of having to find a way to add one later without damaging the rest of the components. When not printed in a specific design for use on a printed wiring board, this type of ultracapacitor could still be cured via a mold to a shape suitable to specific applications. Many polymers maintain some flexibility even after curing, such as the silicone used in this study. The manufacturing process would also be far simpler than that of conventional ultracapacitors.In this work, solid-state ultracapacitors were made by adding the dielectric powder to a two-part polymer (resin and hardener) at the same time. The mixture was then cured in the desired shape at a low temperature until completely set. The addition of the powder to the polymer increased its dielectric properties while leaving most of its physical properties unaltered. At higher powder loading percentages, there were some physical changes as the maximum loading point was approached. To determine the efficiency of these solid-state ultracapacitors, their capacitances were tested, and their dielectric constants (DCs) were measured and compared.
A description is given of a wide dynamic range pulse height analyzer system developed for use on High Energy Cosmic Ray Experiment (HECRE) Balloon Flights. A wide dynamic range of 100,000 is obtained by extending the range of a basic 1024 channel analyzer through the use of multiple ranges and range selection. The system described here contains four 100,000 pulse height analyzers. Each 100,000 pulse height analyzer consists of a group of cordwood welded modules mounted and interconnected on a printed circuit card. Four of these card assemblies, the required clock drive circuitry (discrete components mounted and interconnected on a separate card) and three input-output connectors are interconnected and mounted on the system board.
A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.
As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.
A light source fabrication process to fabricate a customized light source includes attaching a plurality of light emitting diodes to a circuit board, where each light emitting diode is configured to emit light within a same wavelength range. Further, the light source fabrication process includes applying a first phosphor layer to a first set of light emitting diodes of the plurality of light emitting diodes and applying a second phosphor layer to a second set of light emitting diodes of the plurality of light emitting diodes. The phosphor layers are applied to the light emitting diodes using one of a screen printing process and an inkjet printing process. The first phosphor layer is different from and has different optical properties from the second phosphor layer.
This thesis studies drop durability of electronic assemblies when the acceleration vector is oriented at 45° to the out-of-plane direction of the circuit card. The off-axis drop tests are accomplished with a skewed fixture and are conducted as a proxy for multiaxial drop testing. Advanced shock testing and vibration test methods have been developed over the last few decades to better represent real-world field environments during ground-based laboratory testing. However, many of these test methods require expensive and specialized equipment not available in most laboratories. An alternative approach for approximating simultaneous loading along multiple axes on conventional equipment utilizes skewed fixtures which have seen use in off-axis random vibration and drop impact testing. These methods generally rely on the conversion of a uniaxial input load from the test equipment (using a uniaxial drop tower or shaker) into a multiaxial load when resolved in the reference frame of the test article (mounted on a skewed fixture). Skewed fixture design is presented and recommendations for conducting skewed angle drop testing are introduced based on local measurements along the skewed face of the fixture to accurately monitor the impact event. Characterization tests were performed with a skewed fixture, at simultaneous acceleration loads from 500 to 3,000 g in two (in-plane and out-of-plane) directions, while meeting standard time domain tolerances. Upon experimental characterization, drop shock durability tests were conducted on a printed circuit assembly (PCA). Mean drops-to-failure were measured and quantified with Weibull statistics. Dominant solder joint failure modes were identified via failure analysis. Prior work on inclined angle impact testing is limited, and the majority of solder joint interconnect level fatigue studies are conducted considering perpendicular loading normal the circuit card. Low-cycle fatigue curves are generated based on plastic strain and plastic work density within the solder joint. A multiscale nonlinear finite element model is used to relate board-level flexure to solder joint interconnect level plastic strain. A high strain rate solder constitutive model allows for accurate modeling of solder plasticity resulting from high-impact drop shock. Fatigue parameters are computed from the Coffin-Manson relation and Palmgren-Miner damage accumulation. This work serves to apply established low-cycle fatigue methods for conventional drop shock loading (impact normal to circuit card) to non-perpendicular loading with a skewed fixture.
On or about November 10, 1988 an open circuit solder joint was discovered in the Magellan Radar digital unit (DFU) during integration testing at Kennedy Space Center (KSC). A detailed analysis of the cause of the failure was conducted at the Jet Propulsion Laboratory leading to the successful repair of many pieces of affected electronic hardware on both the Magellan and Galileo spacecraft. The problem was caused by the presence of high thermal coefficient of expansion heat sink and conformal coating materials located in the large (0.055 inch) gap between Dual Inline Packages (DIPS) and the printed wiring board. The details of the observed problems are described and recommendations are made for improved design and testing activities in the future.
This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.
Micro-channel-plate-based photo-detectors are unique in being capable of covering very large areas such as those required in elementary particle and nuclear physics, while providing sub-millimeter space resolution, time resolutions of less than 10 picoseconds for charged particles, and time resolutions of 30 psec–50 psec for single photons. In such systems the electronic channel count is a major cost driver. Incorporating a capacitively-coupled anode allows the use of external pickup electrodes with patterns of individual channels optimized for occupancy, rate, and time/space resolution. The signal pickup antenna can be economically implemented as a printed circuit card with a 2-dimensional array of pads for high-occupancy/high-rate applications such as in particle colliders and medical imaging, or a 1-dimensional array of strips for a lower channel count in low-occupancy/low-rate applications such as large neutrino detectors. In this paper we present pad patterns that enhance signal-sharing between pads to lower the channel count per unit area in large-area systems by factors up to 4, while maintaining spatial resolutions of approximately 100 to 200 μ m for charged particles and 400 to 1000 μ m for single photons. Patterns that use multiple signal layers in the signal-pickup board can lower the channel count even further, moving the scaling behavior in the number of pads versus total area from quadratic to linear.
A radiometer that uses aperture synthesis in two dimensions is being built as part of research under NASA's Instrument Incubator Program. The instrument development team consists of engineers at the Goddard Space Flight Center, the University of Massachusetts and Quadrant Engineering. This will be an aircraft instrument operating at L-band which builds on the heritage of ESTAR. The choice of L-band was made because the problem of achieving adequate resolution in space is most critical at this wavelength and because a polarimetric, conical scanning airborne radiometer for future experiments to validate soil moisture and ocean salinity retrieval algorithms is not currently available. The instrument will be designed to fly on the NASA P-3 aircraft in a nadir pointing mode, although other options are possible. The antenna will consist of an array of modules arranged in a rectangular grid. Each module will be comprised of a printed circuit dual-polarized patch and integrated receiver. The distribution of modules within the rectangular array will be adjustable so that several different imaging configurations (e.g. "+","Y", "T") can be employed. The integrated receiver will provide amplification and conversion to IF. The IF signal will be routed to a processor where the required correlations performed. The I and Q channels will be created digitally and the correlations will be done digitally in this processor. The digitization will be done with sufficient bits to study the effects of quantization on radiometer performance. A computer/controller will store the data for conversion to an image and will also perform temperature control and other data interfacing and housekeeping tasks. The instrument is currently in the bread boarding phase of development. A design of the critical components has been completed and hardware is being assembled to test the individual elements. It is expected that a complete 2-channel correlator will be tested by the summer of 2000 and that the complete instrument will be ready for flight tests the following summer (2001).
Ceramic column grid array (CCGA) packages have been used increasingly in logic and microprocessor functions, telecommunications, flight avionics boards, payload electronics boards, engineering navigational and science cameras, electronic assemblies, and other applications, because of their inherent advantages such as high electrical interconnect density, very good thermal and electrical performance, and compatibility with standard surface-mount technology (SMT) packaging assembly processes. Because these advanced electronic packages tend to have less solder-joint strain-relief than do leaded flat-pack electronic packages, the reliability of CCGA packages in challenging thermal environments is a very important consideration for their short- and long-term use in JPL-NASA space missions. In this study, we assembled daisy chains of polyimide printed wiring boards from CCGA-interconnect packages, inspected the boards nondestructively, and then subjected them to thermal cycling to assess their reliability in thermal environments from +125°C to -40°C±25°C. The test hardware consists of a CCGA 1752 package (CN version). The package was divided into four daisy-chained sections that were electrically monitored for their continuity during thermal cycling. The CCGA 1752 package is roughly 45 mm × 45 mm with a 42-mm × 42-mm array of 80%/20% Pb/Sn columns on a 1.00-mm pitch. The resistance of the daisy-chained CCGA interconnects was continuously monitored during thermal cycling in a gaseous nitrogen environment. Electrical continuity resistance measurements as a function of thermal cycling are reported here; tests to date have shown significant change to an open circuit in daisy-chain resistance as a function of thermal cycling. The change in interconnect resistance becomes increasingly noticeable with increasing number of thermal cycles. This paper describes the experimental thermal-cycling test results of CCGA 1752 package reliability testing under an extremely wide temperature range. The first failure was observed at 1479th thermal cycle. We report the thermal-cycle reliability test data for ~2500 thermal cycles.
Langley Research Center s Soluble Imide (LaRC-SI) was discovered by accident. While researching resins and adhesives for advanced composites for high-speed aircraft, Robert Bryant, a Langley engineer, noticed that one of the polymers he was working with did not behave as predicted. After putting the compound through a two-stage controlled chemical reaction, expecting it to precipitate as a powder after the second stage, he was surprised to see that the compound remained soluble. This novel characteristic ended up making this polymer a very significant finding, eventually leading Bryant and his team to win several NASA technology awards, and an "R&D 100" award. The unique feature of this compound is the way that it lends itself to easy processing. Most polyimides (members of a group of remarkably strong and incredibly heat- and chemical-resistant polymers) require complex curing cycles before they are usable. LaRC-SI remains soluble in its final form, so no further chemical processing is required to produce final materials, like thin films and varnishes. Since producing LaRC-SI does not require complex manufacturing techniques, it has been processed into useful forms for a variety of applications, including mechanical parts, magnetic components, ceramics, adhesives, composites, flexible circuits, multilayer printed circuits, and coatings on fiber optics, wires, and metals. Bryant s team was, at the time, heavily involved with the aircraft polymer project and could not afford to further develop the polymer resin. Believing it was worth further exploration, though, he developed a plan for funding development and submitted it to Langley s chief scientist, who endorsed the experimentation. Bryant then left the high-speed civil transport project to develop LaRC-SI. The result is an extremely tough, lightweight thermoplastic that is not only solvent-resistant, but also has the ability to withstand temperature ranges from cryogenic levels to above 200 C. The thermoplastic s unique characteristics lend it to many commercial applications; uses that Bryant believed would ultimately benefit industry and the Nation. "LaRC-SI," he explains, "is a product created in a government laboratory, funded with money from the tax-paying public. What we discovered helps further the economic competitiveness of the United States, and it was our goal to initiate the technology transfer process to ensure that our work benefited the widest range of people." Several NASA centers, including Langley, have explored methods for using LaRC-SI in a number of applications from radiation shielding and as an adhesive to uses involving replacement of conventional rigid circuit boards. In the commercial realm, LaRC-SI can now be found in several commercial products, including the thin-layer composite unimorph ferroelectric driver and sensor (THUNDER) piezoelectric actuator, another "R&D 100" award winner (Spinoff 2005).