SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
A method and apparatus for monitoring a volatile memory in a computer system. Samples of compressed data from locations in the volatile memory in the computer system are read. Data in the volatile memory is reconstructed using the samples of compressed data. The data is an image of the volatile memory. The image enables determining whether an undesired process is present in the volatile memory.
Simple analog control system of digitally controlled acuator uses 'stopped' position of actuator as 'memory' and potentiometer as sensing element during power failure to reload drive circuit to value equal to its last position preceding power loss.
The NASA Charging Analyzer Program (NASCAP) spacecraft charging software developed by Maxwell Technologies has been widely used for the past fifteen to twenty years in satellite design and investigation of spacecraft charging related anomalies. Individual versions of the NASCAP software are available for use in low inclination, low Earth orbit environments (NASCAP[LEO) and geostationary orbit environments (NASCAP/GEO). In addition, the Potentials of Large objects in the Auroral Region (POLAR) code is available for use in LEO polar orbit environments. NASCAP/GEO and POLAR were both written in the 1980's using algorithms appropriate for the computers of the time. They solve the Poisson-Vlasov system for currents and densities assuming limited speed and memory of computer systems standard for the day. In addition, use of the charging models requires individual input files that are not readily transported into the various codes to facilitate comparison of results by the user.
In industrial control systems (ICS), programmable logic controllers (PLC) are the embedded devices that directly control and monitor critical industrial infrastructure processes such as nuclear plants and power grid stations. Cyberattacks often target PLCs to sabotage a physical process. A memory forensic analysis of a suspect PLC can answer questions about an attack, including compromised firmware and manipulation of PLC control logic code and I/O devices. Given physical access to a PLC, collecting forensic information from the PLC memory at the hardware-level is risky and challenging. It may cause the PLC to crash or hang since PLCs have proprietary, legacy hardware with heterogeneous architecture. This paper addresses this research problem and proposes a novel JTAG (Joint Test Action Group)-based framework, Kyros, for reliable PLC memory acquisition. Kyros systematically creates a JTAG profile of a PLC through hardware assessment, JTAG pins identification, memory map creation, and optimizing acquisition parameters. It also facilitates the community of interest (such as ICS owners, operators, and vendors) to develop the JTAG profiles of PLCs. Further, we present a case study of Kyros implementation over Allen-Bradley 1756-A10/B to help understand the framework's application on a real-world PLC used in industry settings. The sample PLC memory dumps are shared with the research community to facilitate further research.
Structure and Evolution of the Universe; Explain structure of the Universe and forecast our cosmic future.
A high-capacity memory with a relatively high data transfer rate and multi-port simultaneous access capability may serve as the basis for new computer architectures. The implementation of a multi-port optical memory is discussed. Several computer structures are presented that might profitably use such a memory. These structures include (1) a simultaneous record access system, (2) a simultaneously shared memory computer system, and (3) a parallel digital processing structure.
Optomechanical systems show great potential as quantum transducers and information storage devices for use in future hybrid quantum networks. In this context, optomechanical strong coupling can enable efficient, high-bandwidth, and deterministic transfer of quantum states. While optomechanical strong coupling has been realized at optical frequencies, it has proven difficult to identify a robust optomechanical system that features the low loss and high coupling rates required for more sophisticated control of mechanical motion. In this paper, we demonstrate strong coupling in a Brillouin-based bulk cavity optomechanical system in both the single-mode and the multimode strong-coupling regime, which leads to a useful device both for applications in quantum information and for investigating decoherence phenomena in bulk acoustic wave resonators. Using nontrivial mode hybridizations in the strong-coupling regime, we create hybridized photonic-phononic modes with lifetimes that are significantly longer than those of the uncoupled system. This surprising lifetime enhancement, which results from the interference of decay channels, showcases the use of multimode strong coupling as a general strategy to control extrinsic decoherence mechanisms. Moreover, phonons supported by such bulk-acoustic-wave resonators have a collection of properties, including high frequencies, long coherence times, and robustness against thermal decoherence, that make this optomechanical system particularly enticing for applications such as quantum transduction and memories. Hence, this system provides access to phenomena in a previously unexplored regime of optomechanical interactions and could serve as an important building block for future quantum devices.
The next major milestone in high performance computing is a sustained rate of one Pflop/s (also written one petaflops, or 10(circumflex)15 floating-point operations per second). In addition to prodigiously high computational performance, such systems must of necessity feature very large main memories, as well as comparably high I/O bandwidth and huge mass storage facilities. The current consensus of scientists who have studied these issues is that "affordable" petaflops systems may be feasible by the year 2010, assuming that certain key technologies continue to progress at current rates. One important question is whether applications can be structured to perform efficiently on such systems, which are expected to incorporate many thousands of processors and deeply hierarchical memory systems. To answer these questions, advanced performance modeling techniques, including simulation of future architectures and applications, may be required. It may also be necessary to formulate "latency tolerant algorithms" and other completely new algorithmic approaches for certain applications. This talk will give an overview of these challenges.
A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.
The MSL Curiosity rover landed on Mars on August~5, 2012. Over time, one of its two computers experienced critical hardware memory failure. This non-volatile NAND flash memory held file system partitions and tunable parameters needed for running rover flight software. The project assembled a design and development team to re-purpose a NOR flash memory hardware chip, only 1.5\% of the size of the NAND, to hold the file systems and parameters. The usable NOR memory required major software changes to accommodate the new limitations of slower access speeds, vastly different physical layout, and smaller size. This presentation discusses the approach, challenges, and outcomes of restoring function to the computer so it can act as a ``lifeboat'' in event of problems with the primary computer.
Photovoltaic (PV) systems are becoming more vulnerable to cyber threats. In response to this emerging concern, developing cyber-secure power electronics converters has received increased attention from the IEEE Power Electronics Society that recently launched a cyber-physical-security initiative. Here this letter proposes a deep sequence learning based diagnosis solution for data integrity attacks on PV systems in smart grids, including dc–dc and dc–ac converters. The multilayer long short-term memory networks are used to leverage time-series electric waveform data from current and voltage sensors in PV systems. The proposed method has been evaluated in a PV smart grid benchmark model with extensive quantitative analysis. As a comparison, we have evaluated classic data-driven methods, including K-nearest neighbor, decision tree, support vector machine, artificial neural network, and convolutional neural network. Comparison results verify performances of the proposed method for detection and diagnosis of various data integrity attacks on PV systems.
Optimal zero-memory regulator for linear system with stochastic jump parameters, considering Bayes and minimax controllers
Topics addressed include: software engineering; university grants; institutes; concurrent processing; sparse distributed memory; distributed operating systems; intelligent data management processes; expert system for image analysis; fault tolerant software; and architecture research.
A system for treating an aneurysm in a blood vessel or vein, wherein the aneurysm has a dome, an interior, and a neck. The system includes a shape memory polymer foam in the interior of the aneurysm between the dome and the neck. The shape memory polymer foam has pores that include a first multiplicity of pores having a first pore size and a second multiplicity of pores having a second pore size. The second pore size is larger than said first pore size. The first multiplicity of pores are located in the neck of the aneurysm. The second multiplicity of pores are located in the dome of the aneurysm.
When learning, the brain modifies individual synaptic connections to reach a desired behavior. Animal and human brains have been shown to be incredibly capable of learning complex and varied functions across a wide variety of tasks. In recent years, artificial neural networks, inspired by human and animal brains, have shown great capabilities in learning a wide variety of difficult tasks. However, artificial neural networks primarily teach themselves through the use of backpropagation, a learning method which has no clear analogue within the brain. Additionally, Artificial Neural Networks primarily use continuous activation functions, which differ significantly from the spiking neuronal behavior present in the brain. In this paper, we discuss and demonstrate a biologically plausible learning method that approximates backpropagation through two techniques on Spiking Neural Networks. First, we show that the local temporal derivatives that are necessary for backpropagation can be approximately recovered through reconstruction using spike timings. Second, we show that through learning during a sleep phase, inspired by neuroscience research into memory replay, the localized parallel feedback path can learn to approximate the derivative through the forward path weight matrix, thus solving the weight transport problem. Lastly, we demonstrate that the combination of these two methods can approach or exceed the accuracy of backpropagation-based methods for a variety of neuromorphic vision tasks while maintaining biological plausibility.
Description of the digital memory and related computer system used at the Palomar Mountain Observatory. The memory was designed to have a large number of pixels, a high capacity for each pixel, and fast access for use with a variety of image sensors. As an image integration and storage device, this memory is shown to possess ideal properties, namely, it is strictly linear, has a wide dynamic range, and the image does not deteriorate with time. The observer has a visual display which enables him to monitor the image as it is being integrated.-
This paper describes results of a numerical analysis evaluating the feasibility of high-temperature shape memory alloys (HTSMA) for active clearance control actuation in the high-pressure turbine section of a modern turbofan engine. The prototype actuator concept considered here consists of parallel HTSMA wires attached to the shroud that is located on the exterior of the turbine case. A transient model of an HTSMA actuator was used to evaluate active clearance control at various operating points in a test bed aircraft engine simulation. For the engine under consideration, each actuator must be designed to counteract loads from 380 to 2000 lbf and displace at least 0.033 inches. Design results show that an actuator comprised of 10 wires 2 inches in length is adequate for control at critical engine operating points and still exhibits acceptable failsafe operability and cycle life. A proportional-integral-derivative (PID) controller with integrator windup protection was implemented to control clearance amidst engine transients during a normal mission. Simulation results show that the control system exhibits minimal variability in clearance control performance across the operating envelope. The final actuator design is sufficiently small to fit within the limited space outside the high-pressure turbine case and is shown to consume only small amounts of bleed air to adequately regulate temperature.
A pattern recognition system has been developed to classify five different aerospace acoustic sources. In this paper the performance of two new classifiers, an associative memory classifier and a neural network classifier, is compared to the performance of a previously designed system. Sources are classified using features calculated from the time and frequency domain. Each classifier undergoes a training period where it learns to classify sources correctly based on a set of known sources. After training the classifier is tested with unknown sources. Results show that over 96 percent of sources were identified correctly with the new associative memory classifier. The neural network classifier identified over 81 percent of the sources correctly.