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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it uses GPUs built in 28 nm technology and achieves about 1000 pJ. Correlators being designed for the SKA telescopes (N = 128 and N = 512) using FPGAs in 16nm technology are predicted to achieve about 100 pJ.

ASIC↗
DOE OSTI2023

Pairwise‐Parallel Entangling Gates on Orthogonal Modes in a Trapped‐Ion Chain

Abstract Parallel operations are important for both near‐term quantum computers and larger‐scale fault‐tolerant machines because they reduce execution time and qubit idling. This study proposes and implements a pairwise‐parallel gate scheme on a trapped‐ion quantum computer. The gates are driven simultaneously on different sets of orthogonal motional modes of a trapped‐ion chain. This work demonstrates the utility of this scheme by creating a Greenberger‐Horne‐Zeilinger (GHZ) state in one step using parallel gates with one overlapping qubit. It also shows its advantage for circuits by implementing a digital quantum simulation of the dynamics of an interacting spin system, the transverse‐field Ising model. This method effectively extends the available gate depth by up to two times with no overhead when no overlapping qubit is involved, apart from additional initial cooling. This scheme can be easily applied to different trapped‐ion qubits and gate schemes, broadly enhancing the capabilities of trapped‐ion quantum computers.

Optics↗
DOE OSTI2020

Fast inference of Boosted Decision Trees in FPGAs for particle physics

We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Event driven readout architecture with non-priority arbitration for radiation detectors

A novel event driven readout architecture, EDWARD (Event Driven with Access and 8 Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz' arbiters, removing the need for an imposed prioritization scheme. It also provides protection against glitches during readout. The system allows not only reading pixel activities, but also retrieving additional data, both analog and digital, from the pixels. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal, seen as an acknowledge token, so there is no dead time between readouts.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A sub-picosecond digital clock monitoring system

We describe a low-cost system designed to monitor wander in digital clocks with a precision of ≤ 1 ps. With this system we have shown that it is possible to track phase variations at the sub-picosecond level by adding noise to a reference clock. As in many cases where a clock is part of a complex distribution network small changes in temperature and other effects can lead to small changes in the clock's phase. As a further demonstration of the system, we have used it to measure the phase changes induced in optical signals in fibers.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

Here, we present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

AstroPix4 — a novel HV-CMOS sensor developed for space based experiments

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm 2 can currently not be reached due to the digital consumption of 3.08 mW/cm 2 , while the analog power consumption of 1.04 mW/cm 2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm 2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A Digital System-On-Chip CO 2 Sensor (Final Report)

The overall goal of the project was to build a low-cost digital CO 2 sensor made of N5’s patented sensing architecture using a digital application specific integrated circuit (ASIC) to reduce the amount of energy usage in residential and commercial buildings. The proposed small form-factor CO 2 monitoring device contains a molecular sieve membrane filter capable of monitoring indoor air quality which indicates the content of CO 2 inside a residential or commercial building.

36 MATERIALS SCIENCE↗
DOE OSTI2022

GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics

Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
NASA NTRS1971

Television multiplexing system

System with single, standard, wideband line transmits ten or more real time TV video data displays over hard wire to recorders more than 22.5 km from source. Digital logic and integrated circuits ensure high reliability and low maintenance. System is adaptable for video sampling applications.

Simpkins, L. G.↗
NASA NTRS1973

Television multiplexing system

A television multiplexing system which includes a circuit that inserts a digital codes sync signal and a digital code into a video signal for identifying the channel is described. The digital sync signal and the digital coded signals are generated by a single crystal controlled clock so that they are always in synchronism with each other. In demultiplexing the signals are utilized for shifting the digital coded signals into a shift register. The shift register, in turn, activates a decoder according to the code stored in the shift register for selecting the proper recording disk or receiver for storing the video signal.

Simpkins, L. G.↗
NASA NTRS1979

Offset compensation for A/D converters

Analog-to-digital (A/D) converter eliminates dc offset in final digitized signal as well as in analog input by using digital feedback for compensation. Circuit could prove useful in data processing applications in which analog-format data are entered at high rates, as in point-of-sale data input systems.

Brokl, S. S.↗
NASA NTRS1979

The 30/20 GHz mixed user architecture development study: Executive summary

The baseline 30/30 GHz satellite communication system, designed for cost-effective communications in the years 1990 to 2000, incorporates on-board satellite demodulation and routing of individual 64 kbps digital voice-grade circuits. This level of routing flexibility is necessary to provide efficient communications to the large number of direct-to-user terminals (DTU) projected. The circuit interfacing hardware is distributed among all the DTU and master control stations. The switching circuitry which provides full interconnectivity between 30 to 45 thousand circuits is in the satellite. The DTU terminal cost, perhaps the largest element in the system cost, represents the largest economic value element of the system because it avoids using terrestrial signal distribution and routing and the charges associated with these functions. Satellite baseline design and power requirements for the system are examined.

Source record↗
NASA NTRS1981

High resolution angular sensor

Specifications for the pointing stabilization system of the large space telescope were used in an investigation of the feasibility of reducing ring laser gyro output quantization to the sub-arc-second level by the use of phase locked loops and associated electronics. Systems analysis procedures are discussed and a multioscillator laser gyro model is presented along with data on the oscillator noise. It is shown that a second order closed loop can meet the measurement noise requirements when the loop gain and time constant of the loop filter are appropriately chosen. The preliminary electrical design is discussed from the standpoint of circuit tradeoff considerations. Analog, digital, and hybrid designs are given and their applicability to the high resolution sensor is examined. the electrical design choice of a system configuration is detailed. The design and operation of the various modules is considered and system block diagrams are included. Phase 1 and 2 test results using the multioscillator laser gyro are included.

Gneses, M. I.↗
NASA NTRS1983

Microprogramed Sequencer for Tunable RF Oscillator

Standard IC chips and digitally tuned oscillator combined. Circuit consists of PROM-based microprogramed control sequencer, which drives group of diode switches to select one of eight tuning capacitors in L-C oscillator. Circuit originally designed to "dither" transmitter frequency of K-band radar at high rates finds application in other areas, as automated test equipment or computer-controlled receiver tuning.

Couch, R. H.↗
NASA NTRS1988

Computer Interface For A Spectroreflectometer

FORTRAN program controls stepping motors and signal-processing electronics via S-100 computer bus. Group of spectroreflectometers modified to provide computer-controlled operation and data collection. Analog and digital signal-processing circuits enable use of computerized automatic data collection and analysis. Previously, spectroreflectometer data recorded on strip charts.

Hurd, William A.↗
NASA NTRS1988

A hardware implementation of a relaxation algorithm to segment images

Relaxation labelling is a mathematical technique frequently applied in image processing algorithms. In particular, it is extensively used for the purpose of segmenting images. The paper presents a hardware implementation of a segmentation algorithm, for images consisting of two regions, based on relaxation labelling. The algorithm determines, for each pixel, the probability that it should be labelled as belonging to a particular region, for all regions in the image. The label probabilities (labellings) of every pixel are iteratively updated, based on those of the pixel's neighbors, until they converge. The pixel is then assigned to the region correspondent to the maximum label probability. The system consists of a control unit and of a pipeline of segmentation stages. Each segmentation stage emulates in the hardware an iteration of the relaxation algorithm. The design of the segmentation stage is based on commercially available digital signal processing integrated circuits. Multiple iterations are accomplished by stringing stages together or by looping the output of a stage, or string of stages, to its input. The system interfaces with a generic host computer. Given the modularity of the architecture, performance can be enhanced by merely adding segmentation stages.

Loda, Antonio G.↗