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Flexure test eliminates failure-prone wafers before further processing. Probability of cracking of silicon solar cells substantially reduced by mechanical proof testing of silicon wafers before further processing, according to report. Report based on study demonstrating weak wafers eliminated by subjecting all wafers in manufacturing batch to biaxial-flexure test.
A device capable of accurate temperature measurement down to 0.01 K of a particular object is discussed. The device is comprised of the following: a heat sink wafer; a first conducting pad bonded near one end of the heat sink wafer; a second conducting pad bonded near the other end of the heat sink wafer; and an oblong doped semiconductor crystal such as germanium. The oblong doped semiconductor crystal has a third conducting pad bonded on its bottom surface with the oblong doped semiconductor crystal bonded to the heat sink wafer by having the fourth conducting pad bonded to the first conducting pad. A wire is bonded between the second and third conducting pads. Current and voltage wires bonded to the first and second conducting pads measure the change in resistance of the oblong doped semiconductor crystal; this indicates the temperature of the object whose temperature is to be measured.
The majority of radio receivers, transmitters, and components operating at millimeter and submillimeter wavelengths utilize rectangular waveguides in some form. However, conventional machining techniques for waveguides operating above a few hundred GHz are complicated and costly. This paper reports on the development of silicon micromachining techniques to create silicon-based waveguide circuits which can operate at millimeter and submillimeter wavelengths. As a first step, rectangular WR-10 waveguide structures have been fabricated from (110) silicon wafers using micromachining techniques. The waveguide is split along the broad wall. Each half is formed by first etching a channel completely through a wafer. Potassium hydroxide is used to etch smooth mirror-like vertical walls and LPCVD silicon nitride is used as a masking layer. This wafer is then bonded to another flat wafer using a polyimide bonding technique and diced into the U-shaped half wavelengths. Finally, a gold layer is applied to the waveguide walls. Insertion loss measurements show losses comparable to those of standard metal waveguides. It is suggested that active devices and planar circuits can be integrated with the waveguides, solving the traditional mounting problems. Potential applications in terahertz instrumentation technology are further discussed.
Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.
The principal objective of this experimental and theoretical research program was to explore the possibility of depositing high quality epitaxial CdTe and HgCdTe at very low pressures through metalorganic chemical vapor deposition (MOCVD). We explored two important aspects of this potential process: (1) the interaction of molecular flow transport and deposition in an MOCVD reactor with a commercial configuration, and (2) the kinetics of metal alkyl source gas adsorption, decomposition and desorption from the growing film surface using ultra high vacuum surface science reaction techniques. To explore the transport-reaction issue, we have developed a reaction engineering analysis of a multiple wafer-in-tube ultrahigh vacuum chemical vapor deposition (UHV/CVD) reactor which allows an estimate of wafer or substrate throughput for a reactor of fixed geometry and a given deposition chemistry with specified film thickness uniformity constraints. The model employs a description of ballistic transport and reaction based on the pseudo-steady approximation to the Boltzmann equation in the limit of pure molecular flow. The model representation takes the form of an integral equation for the flux of each reactant or intermediate species to the wafer surfaces. Expressions for the reactive sticking coefficients (RSC) for each species must be incorporated in the term which represents reemission from a wafer surface. The interactions of MOCVD precursors with Si and CdTe were investigated using temperature programmed desorption (TPD) in ultra high vacuum combined with Auger electron spectroscopy (AES). These studies revealed that diethyltellurium (DETe) and dimethylcadmium (DMCd) adsorb weakly on clean Si(100) and desorb upon heating without decomposing. These precursors adsorb both weakly and strongly on CdTe(111)A, with DMCd exhibiting the stronger interaction with the surface than DETe.
A small silicon p-n junction wafer, when coated with uranium 235, can be used as a compact fission probe for low power flux and power mapping. Because of the inverse relation between the magnitude of a neutron-induced fission pulse and the inherent capacitance of the detecting element (capacitance is proportional to area), the size, and hence the sensitivity, of the semiconductor detector has been limited. New developments in the field of semiconductor detectors have made it possible to fabricate large area detectors which are essentially free from the capacitance effect. However, preliminary results indicate that they are much more susceptible to radiation damage than the detectors described in this report and as such may not be suitable for flux mapping. increasing the sensitivity cannot be accomplished by simply fabricating a larger detector. It has been observed that by combining the silicon p-n junction wafers in a series configuration the capacitance effect can be bypassed, and a fission probe can be made with a resultant increase in sensitivity by a factor of ten while sustaining only a minor decrease in pulse height. Analysis further indicates that for n silicon wafers in series, if n(C(sub i)) + C(sub c)/C(sub b) less than 0.1 where C(sub i) and C(sub c) are the preamplifier input and cable capacitances, respectively, and C(sub b) is the junction capacitance of a single silicon wafer, there should be no substantial reduction in pulse height due to series circuitry.
An alert apparatus for a personal communication device includes a mechanically prestressed piezoelectric wafer positioned within the personal communication device and an alternating voltage input line coupled at two points of the wafer where polarity is recognized. The alert apparatus also includes a variable frequency device coupled to the alternating voltage input line, operative to switch the alternating voltage on the alternating voltage input line at least between an alternating voltage having a first frequency and an alternating voltage having a second frequency. The first frequency is preferably sufficiently high so as to cause the wafer to vibrate at a resulting frequency that produces a sound perceptible by a human ear, and the second frequency is preferably sufficiently low so as to cause the wafer to vibrate at a resulting frequency that produces a vibration readily felt by a holder of the personal communication device.
A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.
We describe progress in the fabrication, characterization, and production of detector arrays for the Atacama Cosmology Telescope (ACT). The completed ACT instrument is specified to image simultaneously at 145, 225, and 265 GHz using three 32x32 filled arrays of superconducting transition edge sensors (TES) read out with time-division-multiplexed SQUID amplifiers. We present details of the pixel design and testing including the optimization of the electrical parameters for multiplexed readout. Using geometric noise suppression and careful tuning of operation temperature and device bias resistance, the excess noise in the TES devices is balanced with detector speed for interfacing with the ACT optics. The design also accounts for practical tolerances such as transition temperature gradients and scatter that occur in the production of multiple wafers to populate fully the kilopixel cameras. We have developed an implanted absorber layer compatible with our silicon-on-insulator process that allows for tunable optical resistance with requisite on-wafer uniformity and wafer-to-wafer reproducibility. Arrays of 32 elements have been tested in the laboratory environment including electrical, optical, and multiplexed performance. Given this pixel design, optical tests and modeling are used to predict the performance of the filled array under anticipated viewing conditions. Integration of the filled array of pixels with a tuned backshort and dielectric plate in front of the array maximize absorption and the focal plane and suppress reflections. A mechanical design for the build of the full structure is completed and we report on progress toward the construction of a prototype array for first light on the ACT.
We describe our current fabrication process for arrays of superconducting transition edge sensor microcalorimeters, which incorporates superconducting Mo/Au bilayers and micromachined silicon structures. We focus on materials and integration methods for array heatsinking with our bilayer and micromachining processes. The thin superconducting molybdenum bottom layer strongly influences the superconducting behavior and overall film characteristics of our molybdenum/gold transition-edge sensors (TES). Concurrent with our successful TES microcalorimeter array development, we have started to investigate the thin film properties of molybdenum monolayers within a given phase space of several important process parameters. The monolayers are sputtered or electron-beam deposited exclusively on LPCVD silicon nitride coated silicon wafers. In our current bilayer process, molybdenum is electron-beam deposited at high wafer temperatures in excess of 500 degrees C. Identifying process parameters that yield high quality bilayers at a significantly lower temperature will increase options for incorporating process-sensitive auxiliary array components (AAC) such as array heat sinking and electrical interconnects into our overall device process. We are currently developing two competing technical approaches for heat sinking large compact TES microcalorimeter arrays. Our efforts to improve array heat sinking and mitigate thermal cross-talk between pixels include copper backside deposition on completed device chips and copper-filled micro-trenches surface-machined into wafers. In addition, we fabricated prototypes of copper through-wafer microvias as a potential way to read out the arrays. We present an overview on the results of our molybdenum monolayer study and its implications concerning our device fabrication. We discuss the design, fabrication process, and recent test results of our AAC development.
A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.
A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.
An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.
A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.
Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.
Wafer reuse techniques help offset the cost of III-V growth substrates by using a single wafer for multiple growths, but costly re-polishing after device removal limits the end benefit. In this work, we present planarization growth by hydride vapor-phase epitaxy (HVPE), a potentially low-cost growth technique, as a method of smoothing rough substrates for subsequent high-quality device growth without the need for polishing. First, we show there is a threshold for allowable substrate roughness without device degradation by comparing devices grown by organometallic vapor-phase epitaxy (OMVPE) on epi-ready polished and pre-polished substrates that did not have the final epi-ready polish. We then demonstrate successful smoothing with HVPE growth on substrates with different surface morphologies, with features ranging from general roughness to large facets. Initial devices grown by HVPE on a pre-polished substate showed no degradation compared to a control wafer, indicating that planarizing rough substrates through HVPE growth is a promising path toward being able to use rough substrates directly for growth, without costly polishing steps.
Ortho-mode transducers (OMT) are a commonly used method of coupling opti-cal signals between waveguides and on-chip circuitry and detectors. While the ideal OMT-waveguide coupling requires minimal disturbance to the waveguide, when used for mm-wave applications the waveguide is often slide though and the OMT probes inserted on a thin support membrane. This interface is a potential source of signal leakage and can lead to signal loss and experimental systematics (e.g. in CMB polarization experiments where lost signal can result in temperature to polarization leakage). Here we report on the development of new OMT- waveguide coupling structures with the goal of reducing leakage at the horn-to-detector-wafer interface. The pixel to pixel optical leakage due to the gap be-tween the coupling waveguide and the backshort is reduced by means of a protrusion that passes through the OMT membrane and connects the waveguide sections on each side of the wafer. High frequency electromagnetic simulations indicate that these protrusions can reduce optical leakage in the gap by ~80% percent, with a ~60% filling factor, respect to an ordinary OMT coupling without protrusion, using designs that are compatible with current fabrication processes. We describe the design of the new coupling structure including the impact of varying two key parameters: wafer to optical coupling gap and protrusion fill factor. Prototype devices have been designed that will characterize the performance of the new design using a relative measurement with varying filling factors. We describe the simulation setup and results, and present a chip layout and sample box designed to perform an initial measurement.
Large area, position sensitive planar germanium detectors offer new opportunities in -ray spectroscopy. For in-beam studies remediating neutron damage is important. This work studied a mechanically cooled circular planar 9 × 1 cm wafer with orthogonal 16 × 16 amorphous germanium strip electrodes. Before neutron irradiation the wafer was heated in-cryostat to above 373 K for more than 24 h in order to test the robustness of the contacts and the mechanical cooler. No deterioration in performance was observed. The detector was then exposed to controlled doses of 2.2 MeV neutrons, produced from the 7 Li(p,n) 7 Be reaction until substantial damage was observed. Averaged over the surface of the wafer, a flux of 1.9(1) x 10 9 n/cm 2 was delivered. The detector then survived thermal cycling and 350 K (~77°C) annealing for 70 h which substantially reduced hole trapping. pulse-height correction is investigated to further mitigate the neutron damage. Higher temperature annealing at 365 K was not successful.