An MOS-transistor-driven laminated-ferrite memory.
High capacity random access magnetic memory storage device combining integrated array of MOS transistors and laminated ferrite memory planes
Gordon, I.↗
SEARCH · Engineering Papers
Results for “random access”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
A satellite communication system using PN codes.
Detectability parameter for measuring performance of multiple and random access satellite communication system using PN codes
Anderson, D. R.↗
Digital data sampling modules, part 1 Final report
Digital data sampling system with random access, distributed data gathering
Source record↗
The SEMS 5L core memory system Final project report, Apr. - Nov. 1969
Design, development, construction, and testing of qualification model for random access memory system for OAO program
Source record↗
A frequency division multiplex technique for transmitting commands
Reliable random access multiplexer is controlled and operated over two twisted-pair telephone lines at distances of 5.6 to 8.0 km with control signals of less than 10 volts rms. Technique adapts to any process or environmental control system where data source is necessary.
Brey, H.↗
Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model
The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.
Source record↗
Plated wire memory subsystem
The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.
Reynolds, L.↗
Table look-up approach to pattern recognition.
The table look-up approach is based on prestoring in fast, random-access, core memory the desired answer (e.g., crop-type) for all combinations of multispectral scanner outputs from selected channels. Specifically, each set of measurements from a given point on the ground is interpreted as that address in core memory where the answer can be retrieved. Substituting the simple retrieval operation for the length y computations required by the conventional approach offers two advantages: (1) the processing time is reduced by more than an order of magnitude; (2) the multispectral scanner data can be processed by computers having minimal sophistication, complexity, and cost. These two advantages may make it possible to use an onboard computer to perform the classification function in flight.
Eppler, W. G.↗
Computational work and time on finite machines.
Measures of the computational work and computational delay required by machines to compute functions are given. Exchange inequalities are developed for random access, tape, and drum machines to show that product inequalities between storage and time, number of drum tracks and time, number of bits in an address and time, etc., must be satisfied to compute finite functions on bounded machines.
Savage, J. E.↗
Memory interface simulator: A computer design aid
Results are presented of a study conducted with a digital simulation model being used in the design of the Automatically Reconfigurable Modular Multiprocessor System (ARMMS), a candidate computer system for future manned and unmanned space missions. The model simulates the activity involved as instructions are fetched from random access memory for execution in one of the system central processing units. A series of model runs measured instruction execution time under various assumptions pertaining to the CPU's and the interface between the CPU's and RAM. Design tradeoffs are presented in the following areas: Bus widths, CPU microprogram read only memory cycle time, multiple instruction fetch, and instruction mix.
Taylor, D. S.↗
Design, processing, and testing of lsi arrays for space station
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.
Lile, W. R.↗
Design relationships for holographic memories.
The maximum capacity of a block-oriented, random-access memory is determined primarily by the geometrical parameters of the lenses required to create a Fourier transform of a spatial bit pattern and to image the reconstructed bits onto a photodetector array. Furthermore, the maximum packing density is determined primarily by the same parameters. Several important relationships are developed that are useful in the preliminary design of holographic memories.
Lugt, A. V.↗
Plated wire memory subsystem
The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.
Carpenter, K. H.↗
Basic memory module
Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.
Tietze, F. C.↗
Design, processing, and testing of LSI arrays for space station
The development of a beam-leaded low power, high performance metal-oxide-semiconductor (MOS), 256-bit random access memory (RAM) was reported. Previous success with the aluminum-gate current-sense version and a silicon-gate voltage-sense version led to the present effort to make a beam-leaded silicon-gate RAM. Some problems unique to the silicon-on-sapphire beam-lead process development are presented. Beam-leaded SOS TA5388 devices using a Si3N4 passivation layer were shown to have good electrical parameters.
Schneider, W. C.↗
Program for the analysis of time series
A digital computer program for the Fourier analysis of discrete time data is described. The program was designed to handle multiple channels of digitized data on general purpose computer systems. It is written, primarily, in a version of FORTRAN 2 currently in use on CDC 6000 series computers. Some small portions are written in CDC COMPASS, an assembler level code. However, functional descriptions of these portions are provided so that the program may be adapted for use on any facility possessing a FORTRAN compiler and random-access capability. Properly formatted digital data are windowed and analyzed by means of a fast Fourier transform algorithm to generate the following functions: (1) auto and/or cross power spectra, (2) autocorrelations and/or cross correlations, (3) Fourier coefficients, (4) coherence functions, (5) transfer functions, and (6) histograms.
Brown, T. J.↗
The advanced OPLE for search and rescue
Recent technological advances have made it possible to develop an advanced OMEGA position location experiment for a global search and rescue application. This application generated some new problem areas such as the OMEGA lane ambiguity, random access, location accuracy, real time processing, and size and weight of the Search and Rescue Communication (SARCOM). This experiment will demonstrate the feasibility of instantaneous alarm and position location by using a relatively inexpensive, battery operated, three-pound package. This package can transmit the alarm and position through a synchronous satellite to a search and rescue station in less than three minutes.
Morakis, J. C.↗
A magnetic bubble domain flight recorder
A feasibility model of an all-electronic bubble memory system has been constructed. It uses a small 60k bit bubble recorder consisting of 6 chips of 10k bits each mounted in three separate packages operating as a FIFO at a 150 KHz bubble data rate. In addition to serving as a direct tape recorder replacement, the bubble recorder can be programmed for random access to each individual chip for ranom block access operation or for self-checking or by-passing any malfunctioning memory chip. Read and write operations can be performed asynchronously from very low frequency up to basic recording field frequency. A large 50M bit prototype is planned.
Chen, T. T.↗