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At least 397 records · Page 22

Finite element computation with parallel VLSI

This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

Mcgregor, J.↗

The Mission Assessment Post Processor (MAPP): A New Tool for Performance Evaluation of Human Lunar Missions

The National Aeronautics and Space Administration s (NASA) Constellation Program paves the way for a series of lunar missions leading to a sustained human presence on the Moon. The proposed mission design includes an Earth Departure Stage (EDS), a Crew Exploration Vehicle (Orion) and a lunar lander (Altair) which support the transfer to and from the lunar surface. This report addresses the design, development and implementation of a new mission scan tool called the Mission Assessment Post Processor (MAPP) and its use to provide insight into the integrated (i.e., EDS, Orion, and Altair based) mission cost as a function of various mission parameters and constraints. The Constellation architecture calls for semiannual launches to the Moon and will support a number of missions, beginning with 7-day sortie missions, culminating in a lunar outpost at a specified location. The operational lifetime of the Constellation Program can cover a period of decades over which the Earth-Moon geometry (particularly, the lunar inclination) will go through a complete cycle (i.e., the lunar nodal cycle lasting 18.6 years). This geometry variation, along with other parameters such as flight time, landing site location, and mission related constraints, affect the outbound (Earth to Moon) and inbound (Moon to Earth) translational performance cost. The mission designer must determine the ability of the vehicles to perform lunar missions as a function of this complex set of interdependent parameters. Trade-offs among these parameters provide essential insights for properly assessing the ability of a mission architecture to meet desired goals and objectives. These trades also aid in determining the overall usable propellant required for supporting nominal and off-nominal missions over the entire operational lifetime of the program, thus they support vehicle sizing.

Williams, Jacob↗

Reusable, Extensible High-Level Data-Distribution Concept

A framework for high-level specification of data distributions in data-parallel application programs has been conceived. [As used here, distributions signifies means to express locality (more specifically, locations of specified pieces of data) in a computing system composed of many processor and memory components connected by a network.] Inasmuch as distributions exert a great effect on the performances of application programs, it is important that a distribution strategy be flexible, so that distributions can be adapted to the requirements of those programs. At the same time, for the sake of productivity in programming and execution, it is desirable that users be shielded from such error-prone, tedious details as those of communication and synchronization. As desired, the present framework enables a user to refine a distribution type and adjust it to optimize the performance of an application program and conceals, from the user, the low-level details of communication and synchronization. The framework provides for a reusable, extensible, data-distribution design, denoted the design pattern, that is independent of a concrete implementation. The design pattern abstracts over coding patterns that have been found to be commonly encountered in both manually and automatically generated distributed parallel programs. The following description of the present framework is necessarily oversimplified to fit within the space available for this article. Distributions are among the elements of a conceptual data-distribution machinery, some of the other elements being denoted domains, index sets, and data collections (see figure). Associated with each domain is one index set and one distribution. A distribution class interface (where "class" is used in the object-oriented-programming sense) includes operations that enable specification of the mapping of an index to a unit of locality. Thus, "Map(Index)" specifies a unit, while "LocalLayout(Index)" specifies the local address within that unit. The distribution class can be extended to enable specification of commonly used distributions or novel user-defined distributions. A data collection can be defined over a domain. The term "data collection" in this context signifies, more specifically, an abstraction of mappings from index sets to variables. Since the index set is distributed, the addresses of the variables are also distributed.

James, Mark↗

Charon Toolkit for Parallel, Implicit Structured-Grid Computations: Functional Design

In a previous report the design concepts of Charon were presented. Charon is a toolkit that aids engineers in developing scientific programs for structured-grid applications to be run on MIMD parallel computers. It constitutes an augmentation of the general-purpose MPI-based message-passing layer, and provides the user with a hierarchy of tools for rapid prototyping and validation of parallel programs, and subsequent piecemeal performance tuning. Here we describe the implementation of the domain decomposition tools used for creating data distributions across sets of processors. We also present the hierarchy of parallelization tools that allows smooth translation of legacy code (or a serial design) into a parallel program. Along with the actual tool descriptions, we will present the considerations that led to the particular design choices. Many of these are motivated by the requirement that Charon must be useful within the traditional computational environments of Fortran 77 and C. Only the Fortran 77 syntax will be presented in this report.

VanderWijngaart, Rob F.↗

Implementation of a High-Speed FPGA and DSP Based FFT Processor for Improving Strain Demodulation Performance in a Fiber-Optic-Based Sensing System

NASA's Aviation Safety and Security Program is pursuing research in on-board Structural Health Management (SHM) technologies for purposes of reducing or eliminating aircraft accidents due to system and component failures. Under this program, NASA Langley Research Center (LaRC) is developing a strain-based structural health-monitoring concept that incorporates a fiber optic-based measuring system for acquiring strain values. This fiber optic-based measuring system provides for the distribution of thousands of strain sensors embedded in a network of fiber optic cables. The resolution of strain value at each discrete sensor point requires a computationally demanding data reduction software process that, when hosted on a conventional processor, is not suitable for near real-time measurement. This report describes the development and integration of an alternative computing environment using dedicated computing hardware for performing the data reduction. Performance comparison between the existing and the hardware-based system is presented.

Farley, Douglas L.↗

The implementation and use of Ada on distributed systems with high reliability requirements

The use and implementation of Ada were investigated in distributed environments in which reliability is the primary concern. In particular, the focus was on the possibility that a distributed system may be programmed entirely in Ada so that the individual tasks of the system are unconcerned with which processors are being executed, and that failures may occur in the software and underlying hardware. A secondary interest is in the performance of Ada systems and how that performance can be gauged reliably. Primary activities included: analysis of the original approach to recovery in distributed Ada programs using the Advanced Transport Operating System (ATOPS) example; review and assessment of the original approach which was found to be capable of improvement; development of a refined approach to recovery that was applied to the ATOPS example; and design and development of a performance assessment scheme for Ada programs based on a flexible user-driven benchmarking system.

Knight, J. C.↗

A programmable power processor for a 25-kW power module

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

Lanier, R., Jr.↗

Configurable Multi-Purpose Processor

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and operate in a launch environment. Additionally, the CTP was designed to interface with the WFF (Wallops Flight Facility) custom-designed transceiver board which is used in the Low Cost TDRSS Transceiver (LCT2) also developed by WFF. The LCT2 s transceiver board demodulates commands received from the ground via the forward link and sends them to the CTP, where they are processed. The CTP inputs and processes data from the inertial measurement unit (IMU) and the GPS receiver board, generates status data, and then sends the data to the transceiver board where it is modulated and sent to the ground via the return link. Overall, the CTP has combined processing with the ability to interface to a GPS receiver, an IMU, and a pulse code modulation (PCM) communication link, while providing the capability to support common interfaces including Ethernet and serial interfaces boarding a relatively small-sized, lightweight package.

Valencia, J. Emilio↗

Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology

A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks.

Biess, J. J.↗

Managing Software Design and Design Changes

Microprocessor-based system for document production work scheduling, and change control and management information aids in design, development, and control of software. Main components Z80 microprocessor, floppydisk and hard-disk drives, and a character printer. System linked to large computer. Major software components are control program monitor (CP/M), text-editing and wordprocessing system, workbreakdown-schedule processor, and data-base management tool.

Loesh, R. E.↗

RTMPL: A structured programming and documentation utility for real-time multiprocessor simulations

The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real time simulations of air-breathing propulsion systems. The Real Time Multiprocessor Simulator (RTMPS) project is aimed at developing a prototype simulator system that uses multiple microprocessors to achieve the desired computing speed and accuracy at relatively low cost. Software utilities are being developed to provide engineering-level programming and interactive operation of the simulator. Two major software development efforts were undertaken in the RTMPS project. A real time multiprocessor operating system was developed to provide for interactive operation of the simulator. The second effort was aimed at developing a structured, high-level, engineering-oriented programming language and translator that would facilitate the programming of the simulator. The Real Time Multiprocessor Programming Language (RTMPL) allows the user to describe simulation tasks for each processor in a straight-forward, structured manner. The RTMPL utility acts as an assembly language programmer, translating the high-level simulation description into time-efficient assembly language code for the processors. The utility sets up all of the interfaces between the simulator hardware, firmware, and operating system.

Arpasi, D. J.↗

Simulating a small turboshaft engine in real-time multiprocessor simulator (RTMPS) environment

A Real-Time Multiprocessor Simulator (RTMPS) has been developed at NASA Lewis Research Center. The RTMPS uses parallel microprocessors to achieve computing speeds needed for real-time engine simulation. This report describes the use of the RTMPS system to simulate a small turboshaft engine. The process of programming the engine equations and distributing them over one, two, and four processors is discussed. Steady-state and transient results from the RTMPS simulation are compared with results from a main-frame-based simulation. Processor execution times and the associated execution time savings for the two and four processor cases are presented using actual data obtained from the RTMPS system. Included is a discussion of why the minimum achievable calculation time for the turboshaft engine model was attained using four processors. Finally, future enhancements to the RTMPS system are discussed including the development of a generalized partitioning algorithm to automatically distribute the system equations among the processors in optimum fashion.

Milner, E. J.↗

Parallel Ada benchmarks for the SVMS

The use of parallel processing paradigm to design and develop faster and more reliable computers appear to clearly mark the future of information processing. NASA started the development of such an architecture: the Spaceborne VHSIC Multi-processor System (SVMS). Ada will be one of the languages used to program the SVMS. One of the unique characteristics of Ada is that it supports parallel processing at the language level through the tasking constructs. It is important for the SVMS project team to assess how efficiently the SVMS architecture will be implemented, as well as how efficiently Ada environment will be ported to the SVMS. AUTOCLASS II, a Bayesian classifier written in Common Lisp, was selected as one of the benchmarks for SVMS configurations. The purpose of the R and D effort was to provide the SVMS project team with the version of AUTOCLASS II, written in Ada, that would make use of Ada tasking constructs as much as possible so as to constitute a suitable benchmark. Additionally, a set of programs was developed that would measure Ada tasking efficiency on parallel architectures as well as determine the critical parameters influencing tasking efficiency. All this was designed to provide the SVMS project team with a set of suitable tools in the development of the SVMS architecture.

Collard, Philippe E.↗

Rendezvous radar for the orbital maneuvering vehicle

This paper describes the development of the Rendezvous Radar Set (RRS) for the Orbital Maneuvering Vehicle (OMV) for the National Aeronautics and Space Administration (NASA). The RRS was to be used to locate, and then provide vectoring information to, target satellites (or Shuttle or Space Station) to aid the OMV in making a minimum-fuel-consumption approach and rendezvous. The RRS design is that of an X-Band, all solid-state, monopulse tracking, frequency hopping, pulse-Doppler radar system. The development of the radar was terminated when the OMV prime contract to TRW was terminated by NASA. At the time of the termination, the development was in the circuit design stage. The system design was virtually completed, the PDR had been held. The RRS design was based on Motorola's experiences, both in the design and production of radar systems for the US Army and in the design and production of hi-rel communications systems for NASA space programs. Experience in these fields was combined with the latest digital signal processor and micro-processor technology to design a light-weight, low-power, spaceborne radar. The antenna and antenna positioner (gimbals) technology developed for the RRS is now being used in the satellite-to-satellite communication link design for Motorola's Iridium telecommunications system.

Locke, John W.↗

Advanced satellite communication system

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

Staples, Edward J.↗

The smart highway project: Smart highways, smart vehicles, smart engineering

The Smart Highway project is a six mile, limited access roadway being built between Interstate 81 and Blacksburg, Virginia. The initial construction segment will be two miles long and is designed to serve as a test bed and test track for Intelligent Transportation Systems (ITS) research. The Center for Transportation Research (CTR) at Virginia Tech is developing three evaluation tools for its ITS research including DYNAVIMTS (a software framework), and the FLASH Lab (a 1/15th scale model highway and vehicle system). The Smart Highway rounds out the Center's evaluation methodology by allowing full scale operational tests, evaluations, and research under both experimental and conventional traffic conditions. Currently under development is a concept for a fully automated highway using a 'Cooperative Infrastructure Managed System' which involves ultra wide band communication beacons installed in the infrastructure with appropriate sensors, receivers and processors on board the vehicles. The project is part of the research program funded by the National Automated Highway System Consortium. The CTR hopes to develop the automated concept to prototype status by 1997. Other smart transportation and smart engineering concepts are proposed. This presentation will address the goals and objectives of the Smart Highway project, overview its status and importance to the region, and identify some of the transportation technology now under development and planned in the future.

Pethtel, Ray D.↗

Modeling Mesoscale Eddies in the North Atlantic Ocean

Ocean modeling plays an important role in understanding the current climatic conditions and predicting the future climate change. Modeling the ocean at eddy-permitting and/or eddy resolving resolutions (1/3 degree or higher) has a two-fold objective. One part is to represent the ocean as realistically as possible, because mesoscale eddies have an impact on the large-scale circulation. The second objective is to learn how to represent effects of mesoscale eddies without explicitly resolving them. This is particularly important for climate models which cannot be run at eddy-resolving resolutions because of the computational constraints. At JPL, a 1/6 degree latitude by 1/6 degree longitude with 37 vertical levels Atlantic Ocean model has been developed. The model is based on the Parallel Ocean Program (POP) developed at Los Alamos National Laboratory (LANL). Using the 256-processor Cray T3D, we have conducted a 40-year integration of this Atlantic eddy-resolving ocean model. A regional analysis demonstrate that many observed features associated with the Caribbean Sea eddies can be realistically simulated by this model. Analysis of this Atlantic eddy-resolving ocean model further suggests that these Caribbean Sea eddies are connected with eddies formed outside the Caribbean Sea at the confluence of the North Brazil Current (NBC) and the North Equatorial Countercurrent. The diagram of the model simulated surface current shows that the Caribbean eddies ultimately originate in the NBC retroflection region, traveling more than a year from the North Brazil coast through the Lesser Antilles into the Caribbean Sea and eventually into the Gulf of Mexico. Additional information is contained in the original.

Chao, Yi↗

Vestibular receptor cells and signal detection: bioaccelerometers and the hexagonal sampling of two-dimensional signals

The inner ear contains sensory organs which signal changes in head movement. The vestibular sacs, in particular, are sensitive to linear accelerations. Electron microscopic images have revealed the structure of tiny sensory hair bundles, whose mechanical deformation results in the initiation of neuronal activity and the transmission of electrical signals to the brain. The structure of the hair bundles is shown in this paper to be that of the most efficient two-dimensional phased-array signal processors.

NASA Program Space Physiology and Countermeasures↗