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At least 397 records · Page 22

The Ocean Colour Climate Change Initiative: I. A Methodology for Assessing Atmospheric Correction Processors Based on In-Situ Measurements

The Ocean Colour Climate Change Initiative intends to provide a long-term time series of ocean colour data and investigate the detectable climate impact. A reliable and stable atmospheric correction procedure is the basis for ocean colour products of the necessary high quality. In order to guarantee an objective selection from a set of four atmospheric correction processors, the common validation strategy of comparisons between in-situ and satellite derived water leaving reflectance spectra, is extended by a ranking system. In principle, the statistical parameters such as root mean square error, bias, etc. and measures of goodness of fit, are transformed into relative scores, which evaluate the relationship of quality dependent on the algorithms under study. The sensitivity of these scores to the selected database has been assessed by a bootstrapping exercise, which allows identification of the uncertainty in the scoring results. Although the presented methodology is intended to be used in an algorithm selection process, this paper focusses on the scope of the methodology rather than the properties of the individual processors.

Climate Change↗

Reconfigurable Very Long Instruction Word (VLIW) Processor

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

Velev, Miroslav N.↗

Selection of a Brine Processor Technology for NASA Manned Missions

The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.

Carter, Donald L.↗

Sample Processor for Life on Icy Worlds (SPLIce): Design and Test Results

We report the design, development, and testing of the Sample Processor for Life on Icy Worlds (SPLIce) system, a microfluidic sample processor to enable autonomous detection of signatures of life and measurements of habitability parameters in Ocean Worlds. This monolithic fluid processing-and-handling system (Figure 1; mass 0.5 kg) retrieves a 50-L-volume sample and prepares it to supply a suite of detection instruments, each with unique preparation needs. SPLIce has potential applications in orbiter missions that sample ocean plumes, such as found in Saturns icy moon Enceladus, or landed missions on the surface of icy satellites, such as Jupiters moon Europa. Answering the question Are we alone in the universe? is captivating and exceptionally challenging. Even general criteria that define life very broadly include a significant role for water [1,2]. Searches for extinct or extant life therefore prioritize locations of abundant water whether in ancient (Mars), or present (Europa and Enceladus) times. Only two previous planetary missions had onboard fluid processing: the Viking Biology Experiments [3] and Phoenixs Wet Chemistry Laboratory (WCL) [4]. SPLIce differs crucially from those systems, including its capability to process and distribute L-volume samples and the integration autonomous control of a wide range of fluidic functions, including: 1) retrieval of fluid samples from an evacuated sample chamber; 2) onboard multi-year storage of dehydrated reagents; 3) integrated pressure, pH, and conductivity measurement; 4) filtration and retention of insoluble particles for microscopy; 5) dilution or vacuum-driven concentration of samples to accommodate instrument working ranges; 6) removal of gas bubbles from sample aliquots; 7) unidirectional flow (check valves); 8) active flow-path selection (solenoid-actuated valves); 9) metered pumping in 100 nL volume increments. The SPLIce manifold, made of three thermally fused layers of precision-machined cyclo-olefin polymer, supports all fluidic components (Figure 1) and integrated microchannels (125 x 250 m). Fluid is pumped by a stepper-motor-driven pump (Lee Co.). The functionality of the integrated MEMS pressure sensor (Honeywell) and passive check valves (Figure 2) were tested in conjunction with our newly designed integral bubble traps (Figure 3) and hydrophobic membrane-based concentrator (Figure 4). The concentrator (initially tested as a standalone component) demonstrated 5-fold vacuum-evaporative concentration. Polyethylene fused bead beds (PEFBBs; 50 porosity) store drylyophilized buffers, calibrants, and fluorescent dyes, and also promote mixing of sample with calibrant, dye, or H2O. Software-controlled automated tests demonstrated successful 1) fluid delivery to each component 2) valve and pump synchronization 3) sample aliquot delivery to instrument interface ports, and 4) rehydration of vacuum-dried fluorescent dye. In Figure 5, fluorescein on PEFBBs was rehydrated for 15 min using a pump-delivered water aliquot; it is displaced as H2O enters the bottom of the channel and pushes the dye into a check valve. Ultimately, SPLIce will fluorescently label amino acids in the sample for microchip-based electrophoretic (MCE) chiral separation and detection to seek and quantify key organic bio-signatures [5]; it will also deliver sample to a microfluidic version of WCL (mWCL) to measure soluble ions and redox-active species.

Life detection↗

NEPP Processor Enclave: Testing Artificial Intelligence & Machine Learning

Computational device families are converging and multiple EEE components are required for a complete HPC subsystem. The components of this “processor enclave” are sensitive to radiation effects and therefore must be characterized for mission assurance. NEPP’s standardized approach to testing the Processor Enclave includes math, graphics, and AI and Machine Learning test vectors and device hardware capable of these applications.

Radiation testing↗

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗

TechEdSat-13: The First Flight of an AI/ML Neuromorphic Processor

Neuromorphic processors, inspired by the wiring of the brain, permit certain classes of Artificial Intelligence/Machine Learning (AI/ML) algorithms to run far more efficiently. Ultimately, such systems will make the small- and nano-satellite platforms even more useful in terms of greatly improved power, communication and internal data management. In addition, on-board processing of images and data will help to not only rapidly interpret the information, but also reduce the amount of data that needs to be transmitted to ground stations. This initial flight experiment uses the Intel/ Loihi processor combined with a custom interface board and three communication channels to run the AI/ML scripts. These will vary with increasing length and complexity during the course of the mission. The algorithms will use the (at first) limited sensor data to ‘learn’ - with comparisons to similar architecture in comparable ground experiments. Some of the applications for successor flights in the TES-n flight series include Cognitive Communications, whereby the overall communication system is optimized per overflight – by optimizing timing and data transmission functions. Lastly, the performance of the Loihi 14nm process technology will be monitored for performance in the LEO radiation environment, thus looking for induced hardware and software errors. This information will help guide future radiation protection techniques to extend the lifetime and overall utility. The TES-13 is a 3U nanosat successfully launched by the Virgin Orbit Launcher-1 on January 13, 2022, and will presage more flights and AI/ML applications to come.

TechEdSat↗

TechEdSat-13: The First Flight of a Neuromorphic Processor

Neuromorphic processors, inspired by the wiring of the brain, permit certain classes of Artificial Intelligence/Machine Learning (AI/ML) algorithms to run far more efficiently. Ultimately, such systems will make the small- and nano-satellite platforms even more useful in terms of greatly improved power, communication and internal data management. In addition, on-board processing of images and data will help to not only rapidly interpret the information, but also reduce the amount of data that needs to be transmitted to ground stations. This initial flight experiment uses the Intel/Loihi processor combined with a custom interface board and three communication channels to run the AI/ML scripts. These will vary with increasing length and complexity during the course of the mission. The algorithms will use the (at first) limited sensor data to ‘learn’ - with comparisons to similar architecture in comparable ground experiments. Some of the applications for successor flights in the TES-n flight series include Cognitive Communications, whereby the overall communication system is optimized per overflight – by optimizing timing and data transmission functions. Lastly, the performance of the Loihi 14nm process technology will be monitored for performance in the LEO radiation environment, thus looking for induced hardware and software errors. This information will help guide future radiation protection techniques to extend the lifetime and overall utility. The TES-13 is a 3U nanosat successfully launched by the Virgin Orbit Launcher-1 on January 13, 2022, and will presage more flights and AI/ML applications to come.

TechEdSat↗

Mixed core processor unit

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

97 MATHEMATICS AND COMPUTING↗

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗

High speed two-dimensional event detection and imaging using an analog interface and a massively parallel processor

A quantitative pulse count (event detection) algorithm with linearity to high count rates is accomplished by combining a high-speed, high frame rate camera with simple logic code run on a massively parallel processor such as a GPU or a FPGA. The parallel processor elements examine frames from the camera pixel by pixel to find and tag events or count pulses. The tagged events are combined to form a combined quantitative event image.

Waugh, Justin↗

Small-world complex network generation on a digital quantum processor

Abstract Quantum cellular automata (QCA) evolve qubits in a quantum circuit depending only on the states of their neighborhoods and model how rich physical complexity can emerge from a simple set of underlying dynamical rules. The inability of classical computers to simulate large quantum systems hinders the elucidation of quantum cellular automata, but quantum computers offer an ideal simulation platform. Here, we experimentally realize QCA on a digital quantum processor, simulating a one-dimensional Goldilocks rule on chains of up to 23 superconducting qubits. We calculate calibrated and error-mitigated population dynamics and complex network measures, which indicate the formation of small-world mutual information networks. These networks decohere at fixed circuit depth independent of system size, the largest of which corresponding to 1,056 two-qubit gates. Such computations may enable the employment of QCA in applications like the simulation of strongly-correlated matter or beyond-classical computational demonstrations.

97 MATHEMATICS AND COMPUTING↗

Characterization of Quantum Frequency Processors

Frequency-bin qubits possess unique synergies with wavelength-multiplexed lightwave communications, suggesting valuable opportunities for quantum networking with the existing fiber-optic infrastructure. Although the coherent manipulation of frequency-bin states requires highly controllable multi-spectral-mode interference, the quantum frequency processor (QFP) provides a scalable path for gate synthesis leveraging standard telecom components. Here, we summarize the state of the art in experimental QFP characterization. Distinguishing between physically motivated “open box” approaches that treat the QFP as a multiport interferometer, and “black box” approaches that view the QFP as a general quantum operation, we highlight the assumptions and results of multiple techniques, including quantum process tomography of a tunable beamsplitter—to our knowledge the first full process tomography of any frequency-bin operation. Our findings should inform future characterization efforts as the QFP increasingly moves beyond proof-of-principle tabletop demonstrations toward integrated devices and deployed quantum networking experiments.

42 ENGINEERING↗

Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh, a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers, a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.

management locality load balance↗